Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent Application Publication by Kim et al. (US 20220336423 A1; Kim)
Regarding claim 1, Kim discloses a light emitting diode comprising:
a first semiconductor layer (153) including a first region, a second region, and a third region (See annotated figure 8 of Kim reference below);
Examiner note – A “region” is broad enough to be any area/volume that may be chosen as there is no restrictions of the boundaries other than the established limitation that each of the first, second, and third regions must include some part of first semiconductor layer each.
an active layer (154) disposed on the third region of the first semiconductor layer, the active layer being absent from the first and second regions of the first semiconductor layer (See annotated Fig. 8 below, where active layer 154 is disposed on the chosen third region, and is absent from the chosen second and first regions);
a first electrode (152) disposed on the first region of the first semiconductor layer (See annotated Fig. 8 below, where first electrode 152 is disposed on the first region of the first semiconductor layer);
a magnetic layer (213) disposed on the second region of the first semiconductor layer (See annotated Fig. 8 below, where when the entire device is connected, the magnetic layer 213 will be disposed on the second region of the first semiconductor layer, Also see Fig. 7, where the Magnetic layer and the rest of the device are directly disposed); and
a second electrode (156) disposed on the third region of the first semiconductor layer (See annotated Fig. 8 below, where second electrode 153 is disposed on the first region of the first semiconductor layer, by being disposed on the active layer 154),
wherein the magnetic layer does not overlap the active layer (Looking at figure 8 of Kim, the magnetic layer 213 does not vertically [in the figure] overlap the active layer 154).
PNG
media_image1.png
420
454
media_image1.png
Greyscale
Figure 1: Annotated Fig. 8 showing chosen regions from the Kim reference.
Regarding claim 2, Kim discloses the light emitting diode of claim 1, and further wherein at least one of a boundary between the first region and the third region and a boundary between the second region and the third region is curved (The boundary between the chosen first region, second region, and third region in the annotated figure are all curved, as one could simply choose the region to be curved so long as it fits the limitations required in the claim).
Regarding claim 3, Kim discloses the light emitting diode of claim 2, and further wherein the boundary between the first region and the third region and the boundary between the second region and the second region are both curved (The boundary between the chosen first region, second region, and third region in the annotated figure are all curved, as one could simply choose the region to be curved so long as it fits the limitations required in the claim)..
Regarding claim 4, Kim discloses the light emitting diode of claim 1, and further wherein the magnetic layer is not in direct contact with the first semiconductor layer (Fig. 7-8, where there is a protective layer (215) between the magnetic layer and the rest of the layers).
Regarding claim 5, Kim discloses the light emitting diode of claim 1, and further comprising:
a protective layer (215) disposed between the second region of the first semiconductor layer and the magnetic layer (Annotated Fig. 8 of Kim above, where protective layer 215 is between the magnetic layer 213 chosen second region of the first semiconductor layer),
wherein the protective layer covers a portion of the first electrode and a portion of the second electrode (Fig. 8, where the protective layer 215 covers the first electrode 156 and the second electrode 152).
Regarding claim 6, Kim discloses the light emitting diode of claim 1, and further wherein the third region includes a first side and a second side opposite to the first side, and
the first region is disposed on the first side of the third region,
the second region is disposed on the second side of the third region, and
the first and second regions are spaced apart from each other.
(Below is an alternate example of regions that are chosen to have the third region to have sides opposite each other [top and bottom] where one side has the first region disposed and the other has the second region disposed. The fourth region can be seen as a null region to give space from the active region and first region).
PNG
media_image2.png
553
586
media_image2.png
Greyscale
Figure 2: Alternative Annotated Fig. 8 showing chosen regions from the Kim reference.
Regarding claim 7, Kim discloses the light emitting diode of claim 1, and wherein heights of the first and second regions are the same, and
a height of the third region is greater than the heights of the first and second regions (Alternative annotated Fig. 8 of Kim below, where the first second and third regions that are chosen to also have the first and second regions that are the same height, and the third height is greater then the first and second regions)
PNG
media_image3.png
428
469
media_image3.png
Greyscale
Figure 3: Alternative Annotated Fig. 8 showing chosen regions from the Kim reference.
Regarding claim 8, Kim discloses the light emitting diode of claim 1, and further comprising:
a second semiconductor layer (155) disposed on the active layer,
wherein the magnetic layer is disposed on the second semiconductor layer (Fig. 8, where when the entire device is connected, the magnetic layer 213 will be disposed on the second semiconductor layer 155, Also see Fig. 7, where the Magnetic layer and the rest of the device are directly disposed)
Regarding claim 9, Kim discloses the light emitting diode of claim 1, and wherein the magnetic layer is spaced apart from the first and second electrodes (Fig. 8, where the magnetic layer 213 is spaced apart from the electrode by at least the protective layer 215).
Regarding claim 10, Kim discloses a light emitting diode, comprising:
a first semiconductor layer (153) including a first region and a second region (See annotated figure 8 of Kim reference below);
Examiner note – A “region” is broad enough to be any area/volume that may be chosen as there are no restrictions of the boundaries other than the established limitation that each of the first, second, and third regions must include some part of first semiconductor layer each.
an active layer (154) disposed on the second region of the first semiconductor layer, the active layer being absent from the first region of the first semiconductor layer (see annotated Fig. 8 from Kim below, where the active layer is disposed on the second chosen region and is not in contact with the first region);
a second semiconductor (155) layer disposed on the active layer (Fig. 8, where the second semiconductor layer 155 is disposed on the active layer 154);
a first electrode (152) disposed on the first region of the first semiconductor layer (see annotated Fig. 8 from Kim below, where the first electrode 152 is disposed on the first region I of the first semiconductor layer 153);
a magnetic layer (214) disposed on the second semiconductor layer (See annotated Fig. 8 below, where when the entire device is connected, the magnetic layer 214 will be disposed on the second semiconductor layer 155, Also see Fig. 7, where the Magnetic layer and the rest of the device are directly disposed); and
a second electrode (156) disposed on the second semiconductor layer (Fig. 8 where the second electrode 156 is disposed on the second semiconductor layer 155, albeit, with multiple layers in-between)
wherein the magnetic layer and the second electrode overlap the second region of the first semiconductor layer (See annotated Fig. 8 of Kim below, where the magnetic layer 214, the second electrode 156, and the chosen second region of the first semiconductor layer, all overlap at least vertically in the figure).
PNG
media_image4.png
430
459
media_image4.png
Greyscale
Figure 4: Alternative Annotated Fig. 8 showing chosen regions from the Kim reference.
Regarding claim 11, Kim discloses the light emitting diode of claim 10, and further wherein a boundary between the first region and the second region is curved (The boundary between the chosen first region and second region in the annotated figure above is curved, as one could simply choose the region to be curved so long as it fits the limitations required).
Regarding claim 12, Kim discloses the light emitting diode of claim 10, and further wherein the magnetic layer is not in contact with the first and second semiconductor layers (Fig. 7-8, where there is a protective layer (215) between the magnetic layer and the rest of the layers).
Regarding claim 13, Kim discloses the light emitting diode of claim 10, and further comprising:
a protective layer (215) disposed between the second semiconductor layer and the magnetic layer (Fig. 8, where protective layer 215 is between the magnetic layer 214 and the second semiconductor layer 155),
wherein the protective layer covers a portion of the first electrode and a portion of second electrode (Fig. 8, where the protective layer 215 covers the first electrode 152 and the second electrode 156).
Regarding claim 14, Kim discloses the light emitting diode of claim 10, wherein the first electrode, the second electrode, and the magnetic layer are disposed on a common straight axis (Fig. 8, Where similar to instant applicant, the axis from a different perspective such as Figs. 5 vs 6 of instant application, an axis moving from left to right in Fig. 8 of instant application will have a common axis for the magnetic layer 214, the first electrode 152, and the second electrode 156), and
the second electrode is disposed between the first electrode and the magnetic layer (When using the left to right axis from Fig. 8, the second electrode 156, will be between the first electrode 152 and the magnetic layer 214).
Regarding claim 15, Kim discloses the light emitting diode of claim 14, wherein the magnetic layer is spaced apart from the second electrode and surrounds the second electrode (When viewing the magnetic layer as including both 213 and 214, the magnetic layer would surround the second electrode 156 from top view and will spaced apart from the second electrode. This is similar to the instant application, where the magnetic layer and the second electrode have vertical separation, so unless there is a very broad understanding of “surround,” applicant would also not have the magnetic layer surrounding the second electrode from the figures).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of United States Patent Application Publication by Yeon et al. (US 20230155030 A1; Yeon).
Regarding claim 17, Kim discloses discloses a display device comprising:
a first semiconductor layer (153) including a first region, a second region, and a third region (See annotated figure 8 of Kim reference below);
Examiner note – A “region” is broad enough to be any area/volume that may be chosen as there is no restrictions of the boundaries other than the established limitation that each of the first, second, and third regions must include some part of first semiconductor layer each.
an active layer (154) disposed on the third region of the first semiconductor layer, the active layer being absent from the first and second regions of the first semiconductor layer (See annotated Fig. 8 below, where active layer 154 is disposed on the chosen third region, and is absent from the chosen second and first regions);
a first electrode (152) disposed on the first region of the first semiconductor layer (See annotated Fig. 8 below, where first electrode 152 is disposed on the first region of the first semiconductor layer);
a magnetic layer (213) disposed on the second region of the first semiconductor layer (See annotated Fig. 8 below, where when the entire device is connected, the magnetic layer 213 will be disposed on the second region of the first semiconductor layer, Also see Fig. 7, where the Magnetic layer and the rest of the device are directly disposed); and
a second electrode (156) disposed on the third region of the first semiconductor layer (See annotated Fig. 8 below, where second electrode 153 is disposed on the first region of the first semiconductor layer, by being disposed on the active layer 154),
wherein the magnetic layer does not overlap the active layer (Looking at figure 8 of Kim, the magnetic layer 213 does not vertically [in the figure] overlap the active layer 154).
PNG
media_image1.png
420
454
media_image1.png
Greyscale
Figure 5: Annotated Fig. 8 showing chosen regions from the Kim reference.
However, while the LED device disclosed by Kim, Kim fails to disclose the manner in which the LED device is integrated into a display device as claim in the instant application.
In a similar field of endeavor, Yeon discloses a similar LED including two electrodes (121 and 129), semiconductor layers (127 and 123), and active active layer (125). There is no mention of a magnetic layer for alignment disclosed by Yeon, however, the structure of the LED in Yeon is similar. Furthermore, Yeon also discloses the structure of the LED being integrated into a display device wherein
a common voltage line (Yeon: VL2; Para. 44, where VL2 is a voltage line for driving many sub-pixels that can be understood to be a common voltage line) and a thin film transistor (Yeon: Fig. 3, also referred to as TFT in disclosure) disposed on a substrate (Yeon: 101);
an insulating layer (Yeon: 117 – Para. 72-73, referred to as a passivation layer) disposed on the common voltage line and the thin film transistor (Yeon: Fig. 12, where the insulating layer 117 is disposed over the common voltage line VL2 and the TFT); and
the first electrode (Yeon: 129) of the light emitting diode is electrically connected to the common voltage line (Yeon: VL2)) through a first connection electrode (Yeon: 212), and
the second electrode (Yeon: 121) of the light emitting diode is electrically connected to the thin film transistor through a second connection electrode (Yeon: 211).
In view of the disclosure of Yeon, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yeon to Kim at the time the instant application was filed to incorporate the LED structure from Kim and integrate it into a display device. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages of integrating the LED device such as the one from Kim into a full display device including TFT and common voltage lines provide in terms of functionality. (Yeon: Para. 6-10)
Regarding claim 18, the combination of Kim and Yeon discloses the display device of claim 17, and further comprising:
a first planarization layer (Yeon: 117) disposed on the insulating layer and surrounding a first portion of a side surface of the light emitting diode (Yeon: Fig. 12); and
a second planarization layer (Yeon: 119) disposed on the first planarization layer and surrounding a remaining second portion of the side surface of the light emitting diode (Yeon: Fig. 12),
wherein the first connection electrode is disposed on the first planarization layer (Yeon: Fig. 12, where first connection electrode 212 is disposed on first planarization layer 117), and
the second connection electrode is disposed on the second planarization layer (Yeon: Fig. 12, where second connection electrode 211 is disposed on second planarization layer 119).
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16, the prior art of Kim does disclose wherein the first semiconductor layer further includes a third region and the active layer being absent from the third region (see above annotated figures from claims 1-10 rejection),
However, the prior art of record fails to show or disclose where “the first electrode including first and second sub electrodes, and the first sub electrode is disposed on the first region, and the second sub electrode is disposed on the third region.” In addition to the other limitations of the claim.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
United States Patent Application Publication by Schuele et al. (US 20230253377 A1; Schuele)
Schuele discusses methods of assembly for LED structures using magnetism for alignment.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights