DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Katoh et al (CN 105765720 A)- citations are made in reference to the paragraph numbers added to the machine translation provided at the end of this office action.
1. An oxide thin film transistor comprising:
a gate electrode (Fig.1A (3) and [0085]) on a center of a substrate (Fig.1A (1) and [0084]);
an active layer (Fig.1A (7) and [0085]) provided on the gate electrode (Fig.1 (11) and [0085]) and the substrate (Fig.1 (10) and [0084]), the active layer (Fig.1 (13) and [0085]) including a metal oxide [0085/0152]; and
a source electrode (Fig.1A (9s) and [0085]) and a drain electrode (Fig.1A (9d) and [0085]) provided on the active layer (Fig.1A (7) and [0085) of both sides of the gate electrode (Fig.1A (3) and [0085]), wherein each of the source electrode (Fig.1A (9s) and [0085/0089-0091]) and the drain electrode (Fig.1A (9d) and [0085/0089-0091]) includes a first metal layer (Fig.1A (9L) and [0089-0091]); and a second metal layer on the first metal layer (Fig.1A (9U) and [0089-0091]).
Claim(s) 1-5, 7-10 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Goto et al (US 2019/0288115).
1. An oxide thin film transistor comprising:
a gate electrode (Fig.1 (11) and [0013]) on a center of a substrate (Fig.1 (10) and [0013]);
an active layer (Fig.1 (13) and [0013]) provided on the gate electrode (Fig.1 (11) and [0013]) and the substrate (Fig.1 (10) and [0013]), the active layer (Fig.1 (13) and [0013]) including a metal oxide [0014]; and
a source electrode (Fig.1 (14) and [0014]) and a drain electrode (Fig.1 (15) and [0014]) provided on the active layer (Fig.1 (13) and [0013]) of both sides of the gate electrode (Fig.1 (11) and [0013]), wherein each of the source electrode (Fig.1 (14) and [0014]) and the drain electrode (Fig.1 (15) and [0014]) includes a first metal layer [0023]; and a second metal layer on the first metal layer [0023].
2. The oxide thin film transistor of claim 1, wherein the first metal layer comprises tungsten [0023-W].
3. The oxide thin film transistor of claim 1, wherein the second metal layer comprises a barrier metal layer [0023-TiN].
4. The oxide thin film transistor of claim 1, wherein the second metal layer comprises titanium [0023-TiN].
5. The oxide thin film transistor of claim 1, wherein the second metal layer further comprises tungsten [0023-W].
7. The oxide thin film transistor of claim 1, wherein the active layer comprises InGaZnO (Fig.1 (13) and [0013-0014]).
8. The oxide thin film transistor of claim 1, further comprising a gate insulation film (Fig.1 (12) and [0013]) between the gate electrode (Fig.1 (11) and [0013]) and the active layer (Fig.1 (13) and [0013]).
9. The oxide thin film transistor of claim 8, wherein the gate insulation film comprises a dielectric material (Fig.1 (12) and [0013-0014]).
10. The oxide thin film transistor of claim 1, wherein the substrate comprises a silicon wafer, glass, or plastic [0013].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katoh et al (CN 105765720 A).
Katoh teaches to forming a laminate of metal alloys to form a source/drain contact region (0089-0091]; however fails to explicitly teach the ratio of claim 6 as cited below:
6. The oxide thin film transistor of claim 1, wherein the second metal layer comprises titanium and tungsten at a component ratio of 1:9.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Katoh’s teachings to include a component ratio of Ti and W of 1:9 as recited in claim 6 because a ratio of the metal materials would result in a conductive metal of good conduction and thermal strength and such ratios in alloys are considered conventional for source drain MOSFETS without producing any unexpected results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yoon (US 2023/0127755); Goto et al (US10896978); Yin et al (2013/0256808) and Miyanaga et al (KR 20190018030) teach similar metal oxide transistors with metal source drain contacts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
8/4/26
Below is a machine translation of the ‘720 reference; paragraph numbers were added by the Examiner for Applicant’s convenience.
Semiconductor Device
Document ID
CN 105765720 A
Date Published
2016-07-13
Inventor Information
Name
City
State
ZIP Code
Country
KATOH, SUMIO
N/A
N/A
N/A
CN
UEDA, NAOKI
N/A
N/A
N/A
CN
Application NO
CN 201480063009 A
Date Filed
2014-08-15
CPC Current
Type
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCI
CPCA
CPCA
CPCA
CPC
H 10 D 86/471
H 10 D 86/423
H 10 D 86/60
H 10 D 64/62
H 10 D 30/6755
H 10 D 30/6745
H 10 D 30/6732
H 10 D 30/6729
H 10 D 30/6755
H 10 D 64/62
H 10 D 30/6729
H 10 D 86/481
H 10 D 86/423
H 10 D 86/60
G 02 F 1/1368
H 10 B 20/25
H 10 B 20/25
G 09 G 3/3655
G 02 F 1/1368
G 09 G 2300/0842
G 09 G 2300/0426
G 09 G 2300/08
Date
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2025-01-01
2013-01-01
2023-02-01
2023-02-01
2013-01-01
2013-01-01
2013-01-01
2013-01-01
2013-01-01
Abstract
This semiconductor device is provided with a memory transistor (10A) which can be irreversibly changed from a semiconductor state where a drain current (Ids) is dependent on the gate voltage (Vg) to a resistor state where the drain current (Ids) is not dependent on the gate voltage (Vg). The memory transistor (10A) comprises a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure including a first drain metal layer (9d1) that is formed of a first metal having a melting point of 1,200 DEG C or more and a second drain metal layer (9d2) that is formed of a second metal having a lower melting point than the first metal. When viewed from the normal direction of the surface of a substrate, a part (P) of the drain electrode (9d) overlaps both the metal oxide layer (7) and the gate electrode (3), and the part (P) of the drain electrode (9d) contains the first drain metal layer (9d1) but does not contain the second drain metal layer (9d2). 9d2).
Description
INVENTION-TITLE
Technology field
The invention relates to a semiconductor device having a storage transistor.
Background technology
as can be used as a ROM (read only memory) memory element, always people provides element (hereinafter called "memory transistor") has a transistor structure.
For instance, patent document 1 discloses a non-volatile memory transistor having a MOS transistor structure. the memory transistor by applying high electric field to the gate insulating film dielectric breakdown thereof for writing. In addition, patent document 2 discloses a storage transistor, wherein using the change of the threshold voltage due to the gate by applying a predetermined write voltage is generated.
Therefore, patent documents of the applicant 3 a can reduce the power consumption, compared with the existing technology of new-type non-volatile memory transistor. metal oxide semiconductor is used as an active layer (channel) in the memory transistor, capable of using joule heat generated due to drain current, irreversibly change is independently exhibits ohmic resistance characteristics and gate voltage of the resistance state. By using such a memory transistor, it can make the writing voltage lower than for patent document 1, 2 in voltage. In addition, in the present specification, the change the oxide semiconductor of the storage transistor is resistor state of motion called "write". In addition, after writing because the metal oxide semiconductor resistor, the memory transistor action, but is not as a transistor resistor change after in this specification it is referred to as a "memory transistor". Similarly, after the change is a resistor, always using the transistor structure of a gate electrode, a source electrode, a drain electrode, an active layer, a channel region such as name. patent document 3 recorded in the memory transistor such as techniques for forming on the active matrix substrate of the liquid crystal display device.
prior art document
Patent Document
Patent literature 1: US Patent No. 6775171 specification
patent document 2: Japanese special platen 11-97556 number gazette
Patent literature 3 international public No. 2013/080784
invention contents
technical problem to be solved by the invention
the inventor of the invention the active layer comprises a metal oxide containing structure of the memory transistor to research from various angles. The results showed that, if attempting to further shorten the writing time of the memory transistor, the lower the current of the electrode structure may be unable to obtain high reliability. for details on the problem.
The purpose of embodiments of the present invention is compared with the existing technology to improve the reliability of the semiconductor device having a memory transistor.
the technical means to solve the technical problem
The invention claims a semiconductor device, comprising a substrate and at least one memory transistor supported on the substrate, the at least one memory transistor is from the drain current Ids depending on the gate voltage Vg of semiconductor state irreversibly change to drain current Ids does not depend on the gate voltage (Vg) of the resistance state of the memory transistor, the at least one memory transistor includes a gate electrode, a metal oxide layer disposed between the gate electrode and the metal oxide layer of the gate insulating film and the electric source electrode and drain electrode is connected with the metal oxide layer. the drain electrode has a laminated structure comprising the first drain electrode metal layer and a second drain metal layer, the first metal of the first drain metal layer whose melting point is more than 1200 ℃; the second drain metal layer having a melting point lower than the first metal and the second metal; in the normal direction from the surface of the substrate, a portion of the drain electrodes is overlapped with the metal oxide layer and the gate electrode, the portion of the drain electrode comprises the first drain electrode metal layer and not comprising the second drain electrode metal layer.
In one embodiment, the source electrode has a laminated structure comprising a first source metal layer and a second source metal layer, the first source electrode metal layer containing the first metal, the second source metal layer comprising the second metal. in the normal direction from the surface of the substrate, a portion of the source electrode is overlapped with the metal oxide layer and the gate electrode, the portion of the source electrode comprises the first source electrode metal layer and the second source electrode metal layer.
In one embodiment, the source electrode has a laminated structure comprising a first source metal layer and a second source metal layer, the first source electrode metal layer containing the first metal, the second source metal layer comprising the second metal. in the normal direction from the surface of the substrate, a portion of the source electrode is overlapped with the metal oxide layer and the gate electrode, the portion of the source electrode comprises the first source electrode metal layer and does not comprise the second source electrode metal layer.
In one embodiment, the upper surface of the first drain electrode metal layer in direct contact with the metal oxide layer.
In one embodiment, the lower surface of the first drain electrode metal layer in direct contact with the metal oxide layer.
In one embodiment, the gate electrode is located on the metal oxide layer of the substrate side.
In one embodiment, the first drain electrode metal layer and the second drain electrode metal layer stacked in this order from the substrate side.
In one embodiment, when viewed from the normal direction of the substrate, the metal oxide insulation layer in the gate insulating film overlapped with the gate electrode and a part of the source electrode and the drain electrode has a U shape.
In one embodiment, the first metal is selected from the group consisting of W, Ta, Ti, Mo, and Cr metal or alloy thereof.
In one embodiment, the melting point of the second metal is less than 1200 ℃.
In one embodiment, the second metal is a metal selected from the group consisting of Al and Cu.
In one embodiment, the metal oxide layer containing In, Ga, and Zn.
In one embodiment, the metal oxide layer comprises a crystalline portion.
a plurality of memory transistor memory transistor ST In one embodiment, the at least one memory transistor includes the semiconductor state and the resistive state of the memory transistor.
In one embodiment, further comprises other transistor semiconductor layer including metal oxide is supported on the substrate. the metal oxide layer on the semiconductor layer and the memory transistor of the other transistor formed by oxide semiconductor film, the source electrode, and the drain electrode of the other transistor has a laminated structure comprising a first metal layer and a second metal layer, the first metal layer containing the first metal, the second metal layer comprising the second metal. in the normal direction from the surface of the substrate, a part of the drain electrode of the other transistor is overlapped with the gate electrode of the other transistor and the metal oxide layer are both the drain electrode of the other transistor of the first portion comprises the first metal layer and the second metal layer.
In one embodiment, the semiconductor device is an active matrix substrate, comprising a display area, the display area comprises multiple pixel electrodes and pixel transistor is respectively electrically connected with the corresponding pixel electrode of the plurality of pixel electrodes, and a peripheral region; the peripheral region comprises a plurality of circuit configurations in the region outside the display region, the plurality of circuit comprises a memory circuit with the at least one memory transistor of the pixel transistor and the plurality of transistors constituting the plurality of circuit in the peripheral region of at least one of with the at least one memory transistor of the metal oxide layer using the oxide semiconductor film to form a semiconductor layer.
invention
According to one embodiment of the present invention, provided with a metal oxide layer as the active layer and using from a semiconductor state to change the resistive state of the memory transistor in the semiconductor device, which can suppress the memory transistor for writing drain electrode melting caused by the heat generated. Therefore, it can restrain the heat that the memory transistor from being damaged or broken down caused by writing, so it can improve the reliability of the semiconductor device.
Description according to claim claimimages
In FIG. 1, (a) and (b) 10A cross-sectional view and plan views of memory transistors are respectively in the semiconductor device of the first embodiment.
FIG. 2 is a example configuration diagram in the first embodiment a single storage unit storage circuit.
In FIG. 3, (a) and (b) are respectively a sectional view and a plan view of the memory transistor of the embodiment 10 (1), (c) is a view of after writing of the memory transistor 10 (1).
In FIG. 4, (a) and (b) are reference examples of the memory transistor 10 (2) cross-section diagram and a plan view, (c) is a view of after writing of the memory transistor 10 (2).
In FIG. 5, (a) is an example description 1002 a plan view of an active matrix substrate of the first embodiment, (b) is an example that an active matrix substrate 1002 in the pixel transistor 10T of the cross-sectional view, (c) is an example that uses the active matrix substrate 1002 of the cross-sectional view of the display device 2001.
FIG. 6 is example explanation module structure of the liquid crystal display device 2001 FIG.
In FIG. 7, (a) and (b) is a schematic diagram of the structure of a pixel circuit composing storage unit and liquid crystal display devices 60a to 60c of the nonvolatile storage device 2001.
FIG. 8 is used to illustrate the first embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1002) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 9 is used to illustrate the first embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1002) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 10 is used to illustrate the first embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1002) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 11 is used to illustrate the first embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1002) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 12 is used to illustrate the first embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1002) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 13 is used to illustrate the first embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1002) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
In FIG. 14, (a) represents an Ids-Vgs characteristic of the memory transistor 10A in the initial state (semiconductor state) of the graph, and (b) represents an Ids-Vds characteristic in an initial state of the storage transistor 10A of FIG.
In FIG. 15, (a) represents an Ids-Vgs characteristic of the memory transistor 10A of the resistor in the state graph, and (b) represents an Ids-Vds characteristic of the memory transistor 10A of the resistor in the state of FIG.
FIG. 16 is the memory transistor in the write back 10A under the condition of Vgs=0V near the origin of the Ids-Vds characteristic of the amplified image.
FIG. 17 is a 10A Ids-Vgs characteristic of the memory transistor and before writing the overlay representation.
FIG. 18 is a representation of a memory transistor and before writing 10A differential resistance (dVds/dIds, unit: Omega mu m) and the drain voltage Vds of the relationship of FIG.
FIG. 19 shows a memory transistor 10A of writing time (unit: m seconds) the unit drain current (unit: um) relation to one example.
FIG. 20 is a plan shape channel region of a memory transistor view showing the relation between the writing time.
In FIG. 21, (a) and (b) is an example explaining the first embodiment of the other memory transistor structure of the plan view and cross-sectional view.
In FIG. 22, (a) and (b) are respectively 10C a plan view and cross-sectional view of a memory transistor representing the second embodiment of the semiconductor device.
FIG. 23 is used to illustrate the second embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1003) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 24 is used to illustrate the second embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1003) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 25 is used to illustrate the second embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1003) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 26 is used to illustrate the second embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1003) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 27 is used to illustrate the second embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1003) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
FIG. 28 is used to illustrate the second embodiment of the manufacturing method of the semiconductor device (active matrix substrate 1003) a view showing a process of (a) and (b) is a sectional view, (c) is a plan view.
In FIG. 29, (a) and (b) are respectively 10D plan view and cross-sectional view of a memory transistor representing the third embodiment of the semiconductor device.
FIG. 30 is a method for manufacturing a semiconductor device (active matrix substrate 1004) explanation view showing a process of a third embodiment, (a) and (b) is a sectional view, (c) is a plan view.
FIG. 31 is a method for manufacturing a semiconductor device (active matrix substrate 1004) explanation view showing a process of a third embodiment, (a) and (b) is a sectional view, (c) is a plan view.
FIG. 32 is a method for manufacturing a semiconductor device (active matrix substrate 1004) explanation view showing a process of a third embodiment, (a) and (b) is a sectional view, (c) is a plan view.
FIG. 33 is a method for manufacturing a semiconductor device (active matrix substrate 1004) explanation view showing a process of a third embodiment, (a) and (b) is a sectional view, (c) is a plan view.
FIG. 34 is a method for manufacturing a semiconductor device (active matrix substrate 1004) explanation view showing a process of a third embodiment, (a) and (b) is a sectional view, (c) is a plan view.
In FIG. 35, (a) to (c) is an example to illustrate the embodiment of the invention of the other memory transistor structure of the plan view and sectional view.
In FIG. 36, (a) to (c) is an example to illustrate the embodiment of the invention of the other memory transistors structure of sectional view.
Preferred Embodiment
firstly, the inventor of the present invention is directed to using the structure through research of the storage transistor (patent document 3) from a semiconductor state to change resistive state to get insight.
writing of the memory transistor is performed such, that by using the drain current (write current) generated by joule heat, low resistance metal oxide layer as the memory transistor active layer, thereby performing writing. when writing, the metal oxide layer of the memory transistor will generate heat.
heat (calorific value) generated by the metal oxide layer if further increasing the writing, it is possible to further shorten the writing time. heating by supplying more power of the memory transistor is increased. However, there are the following problems when the productivity is increased.
in the n-channel memory transistor when writing, the productivity especially in metal oxide layer (channel region) and the drain electrode increases. a metal oxide layer of a drain-side there is partial to the condition of high temperature, such as more than 1000 ℃. Therefore, the memory transistor has a bottom gate structure under the condition that the upper surface of the metal oxide layer as the drain electrode if provided by aluminium, copper and lower melting point of the metal forming the metal layer, the metal will possibly caused by writing by heat melting. As a result, the drain electrode and the metal oxide layer are not conducted to produce source-metal oxide layer-drain current path is broken (not then a current flow between the source and the drain) damage, such as possible memory transistor is broken. Therefore, the normal read operation of the memory transistor after writing can become difficult.
On the other hand, current known a problem like this, namely, in the thin film transistor (oxide semiconductor TFT) metal oxide layer as the active layer, if the metal oxide layer and the aluminum (Al) layer or a copper (Cu) layer in direct contact, then there is contact resistance between them increases, or Al or Cu diffusion to the metal oxide layer caused by the TFT characteristics is reduced. In order to solve the problem, the user provides the technology (e.g., Japanese special opening 2010-123923 number gazette) forming a Ti layer as a barrier metal layer between the source electrode and the drain electrode and the metal oxide layer composed of Al or Cu of. In addition, the invention further claims technology (e.g., Japanese special opening 2010-123748 number gazette) laminated film using side are stacked from the metal oxide layer a Ti film and the Al alloy film as a source electrode and the drain electrode of the metal wiring film. if using the patent document provided by the electrode or wiring, such as Al, Cu of lower melting point metal does not directly contact with the metal oxide layer. However, the inventors confirmed through research, as long as metal of lower melting point located above the metal oxide layer, even without direct contact with the metal oxide layer when writing, there occurs possibility of melting. vice versa, for Ti and so on with high melting point metal, the inventors also confirmed that, even if it is located on the metal oxide layer, also will not heat when melting writing occurs.
Based on the insight, the inventor of the present application, the drain electrode is formed of a metal storage transistor is high by using the melting point of oxide layer located on the metal part, so that it is free of low melting point metal, so as to solve the above problem caused due to heating when writing so as to finish the invention. According to this scheme, when inhibiting writing of heat causes the reliability of the memory transistor is reduced at the same time. Compared with the existing technology, the invention shortens writing time.
With reference to drawings embodiments of the semiconductor device of the invention will be described.
(first embodiment)
FIG. 1 (a) is a 10A cross-sectional view of a memory transistor representing the implementation way of the semiconductor device, FIG. 1 (b) is a (plan view) of the storage transistor 10A plan view. FIG. 1 (a) represents the section structure of the I-I ' line in FIG. 1 (b).
The semiconductor device of the embodiment includes a substrate 1 and a support on the substrate 1 of the memory transistor 10A. memory transistor 10A is, for example, an n-channel type memory transistor.
active layer (hereinafter called "metal oxide layer") of storage transistor 10A includes a gate electrode 3, metal oxide containing 7, configuring the gate electrode 3 and the metal oxide layer 7 between the gate insulating film 5, and the metal oxide layer 7 is electrically connected to a source electrode 9 s and a drain electrode 9d. when viewed from the normal direction of the substrate 1, at lest one part of the metal oxide layer 7 are overlapped through a gate insulating film 5 and the gate electrode 3. In the example shown in FIG. 1, a gate electrode 3 is disposed on the metal oxide layer 7 of the substrate 1 side (bottom-gate structure). can be source electrode 9 s contact with a portion of the metal oxide layer 7, the drain electrode 9d and the metal oxide layer 7 in addition to a portion of the contact structure.
area of the metal oxide layer 7 in contact with the source electrode 9 s (or electrically connected) called "source contact region, and the drain electrode 9d contact (or electrically connected) region is called" drain contact region ". when viewed from the normal direction of the substrate 1, the metal oxide layer 7 via a gate insulating film 5 and the gate electrode 3 overlap with each other, and located between the source contact region and the drain contact region becomes the channel region 7c. under the source electrode 9 s and the drain electrode 9d contact with the upper surface of the metal oxide layer 7, when viewed from the normal direction of the substrate 1, metal oxide layer 7, the source electrode 9 s and the drain electrode 9d between the region becomes the channel region 7c.
drain electrode 9d has a laminated structure, the laminated structure comprising a first drain metal formed by the first metal layer 9d1 and the second drain metal layer having a melting point lower than the first metal and the second metal form 9d2. "formed by first metal (second metal) or" meaning is, mainly comprising the first metal (or the second metal). Further, the first metal or the second metal may be a metal simple substance, or the alloy.
first drain metal layer 9d1 of the first metal is melting point is more than 1200 ℃, preferably more than 1600 ℃ of the metal (hereinafter referred to as "first metal"). The first metal may be a metal simple substance, or the alloy. as the first metal, capable of using Ti (titanium, melting point: 1667 ℃), for example, Mo (molybdenum, melting point: 2623 ℃), Cr (chrome, melting point: 1857 ℃) and W (tungsten, melting point: 3380 ℃), Ta (tantalum, melting point: 2996 ℃) or alloys thereof, and the like. the second drain electrode of the second metal containing metal layer 9d2 has a lower melting point than the first metal metal (hereinafter called "second metal"). the melting point of the second metal may be lower than 1200 ℃, such as less than 700 ℃. as the second metal, for example, can be Al (aluminum, melting point: 660 ℃), Cu (copper, melting point: 1083 ℃) and so on.
source electrode 9 s and drain electrode 9d can be formed by a common conductive film. in the example shown, the source electrode 9 s and the drain electrode 9d using a common laminated film forming the common laminated film comprises a first metal film 9 L formed by the first metal and the second metal is formed by the second metal film 9U. Thus, the source electrode 9 s includes a first metal film 9 L and second metal film 9U of the laminated structure. the layers are composed of the first metal film 9 L and second metal film 9U formed in the source electrode 9 s is called the first source metal layer 9s1 and the second source metal layer 9s2. Similarly, the drain electrode 9d has a laminated structure, the laminated structure comprising a second drain metal layer is composed of a first metal film 9 L formed by the first drain metal layer 9d1 and the second metal film 9U formed of 9d2.
the first metal film 9 L and second metal film 9U is a metal mainly including the conductor layer may not be a layer composed of metal simple substance, but includes an alloy layer, a metal nitride layer, a metal silicide layer, and so on.
when it is observed from normal direction of surface of substrate 1, a drain electrode 9d has overlapped with the gate electrode 3 and the metal oxide layer 7 both part P. the drain electrode 9d is overlapped with the gate electrode 3 and the metal oxide layer 7 both part P comprises a first drain metal layer 9d1 (first metal film 9 L), and does not include the second drain metal layer 9d2 (second metal film 9U). the part P can be formed only by the first drain metal layer 9d1, also can comprises the high melting point metal layer 9d1 other than the first drain electrode metal layer.
memory transistor of this exemplary embodiment 10A is from the drain current Ids dependent irreversibly change non-volatile storage element to the drain current Ids does not depend on the gate voltage Vgs of the state (called "resistive state) of the gate voltage Vgs of the state (referred to as" semiconductor state "). drain current Ids is the storage source electrode 9 s of transistor 10A and the drain electrode 9d (between the source-drain current flowing), the gate voltage Vgs is the gate electrode 3 and the source electrode 9 s (between gate-source) voltage.
the change of state for example by source-drain semiconductor state (initial state) of the memory transistor 10A applying a predetermined write voltage Vds, and applying a predetermined gate voltage between the gate-source is generated. by applying the write voltage Vds, in the metal oxide layer 7 for forming a channel portion (channel region) 7c with a current (writing current) flows, Joule heat is generated. due to the Joule heat, the metal oxide layer 7 in the channel region 7c is low resistance. As a result, as the gate voltage Vgs irrespective of exhibits ohmic resistance characteristics of the resistance state. reason of low resistance oxide semiconductor occurs although further in the expiscates, but can be considered to be caused by Joule heat, oxygen contained in the oxide semiconductor diffused to the outside of the channel region 7c, so as to cause the channel region of oxygen vacancy 7c from increasing, to generate current-carrying electrons. In addition, it can generate memory transistor of such a state change of patent documents of the applicant 3, the applicants have not been published patent application, Japanese special number 2012-137868 and Japanese gazette No. 2012-231480, is recorded. For the purpose of reference, the specification for all disclosed contents of these documents.
As described above, writing of the memory transistor 10A by Joule heat caused by write current. on the said, joule heat on the metal oxide layer 7 to form a channel region 7c of the drain side end becomes particularly high. Accordingly, without configuring the second drain metal layer 9d2 at high Joule heat near the drain side end in the embodiment. More specifically, when it is observed from normal direction of surface of substrate 1, a drain electrode 9d containing high melting point metal of the first drain electrode metal layer 9d1 to overlap with the gate electrode 3 and the metal oxide layer 7 both are structured to define channel region 7c. On the other hand, the lower melting point of the metal of the second drain metal layer 9d2 is not disposed on the metal oxide layer 7, it is possible to suppress the heat generated by the write causes a second drain metal layer 9d2 of the metal melt. Therefore, the invention can restrain the metal melting causes the memory transistor 10A is broken or deformed.
In this embodiment, when it is observed from normal direction of surface of substrate 1, a metal oxide layer 7 overlapped with the gate electrode 3, but the metal oxide layer 7 can also be configured as at least a portion thereof overlaps with the gate electrode 3. At this time, as long as the second drain electrode metal layer 9d2 are not located on the metal oxide layer 7 in the gate electrode 3 partially overlap, it can obtain the same effect. For example, the second drain metal layer 9d2 only when it is observed from normal direction of surface of substrate 1 not with the metal oxide layer 7 and the gate electrode 3 both overlap and can be overlapped with either.
In addition, the drain electrode 9d is a double layer structure composed of a first drain metal layer 9d1 and the second drain metal layer 9d2 is formed, but may also be comprised of other conductive layers 3 of more than one layer. a first drain metal layer 9d1 may contact with the upper surface of the metal oxide layer 7. in the first drain electrode metal layer 9d1 using, for example, Ti, Mo layer, if present, by configuring such that the first drain metal layer 9d1 contact with the metal oxide layer 7 can reduce the contact resistance. Additionally, between the metal oxide layer 7 and the first drain electrode metal layer 9d1 may also form a contact layer or other conductive layer.
the n-channel memory transistor under the condition that drain the upstream side of the flowing direction of the current Ids is the drain, the downstream is the source electrode. In this specification, "source electrode" refers to the source of the active layer (here is a metal oxide layer (7) on one side of an electrode electrically connected, may be part of a wiring (source wiring). Typically, the "source electrode" not only includes direct contact with the active layer of the electrode, further comprising the contact part of one side at the near part. For example, when electrically connected under the active layer in a portion of the source wiring, the source electrode includes a source wiring in the transistor forming part of the storage area. Alternatively, the "source electrode" can include a source wiring and other elements or other wiring connection from the active layer in contact with the contact portion. Similarly, the "drain electrode" refers to the drain of active layer (here is a metal oxide layer (7) on one side of an electrode electrically connected, can be part of a wiring. a drain-side drain electrode not only comprises the active layer directly contacts the contact part further comprises at the near part. electrically connected to the active layer of drain electrode on one side of a part of the wire under the condition of "drain electrode" includes the wiring located in the partial area of the memory transistor is formed. For example, can contain wiring and other elements or other wiring connection from the active layer in contact with the contact portion. In this embodiment, the drain electrode 9d of the part P is a first drain metal layer 9d1 and the single-layer structure does not comprise the second drain metal layer 9d2 (or layer n (n: a natural number of 2 or more)), other parts of the drain electrode comprises the first drain electrode metal layer 9d1 and the second drain metal layer 9d2 of the double-layer structure (or the (n + 1) layer structure).
when it is observed from normal direction of surface of substrate 1, the source electrode 9 s may have overlapping with the metal oxide layer 7 and the gate electrode 3 both part of Q. the source electrode 9 s is overlapped with the metal oxide layer 7 and the gate electrode 3 both of moiety Q not only contains the first source electrode metal layer 9s1 also can include a second source metal layer 9s2. the metal oxide layer 7 of the channel region 7c of the source side, productivity caused by write current less than the drain side. Therefore, even when the 7c is disposed near the second source metal layer 9s2 and the second metal of the second source metal layer 9s2 which is not easily melted, not easily due to heating caused by writing memory transistor 10A is damaged. In this embodiment, the source electrode 9 s and the drain electrode 9d to the channel region 7c on one side of the end of different structures, can furthest enjoy by using higher conductivity of the metal layer (Al layer) benefits while reducing damage caused by writing of heating.
In addition, as after the source electrode part 9 s may also comprise a first source metal layer 9s1 but not a second source metal layer 9s2. Thus, it is possible to more reliably reduce damage caused by heating is written.
in the example shown, when viewed from normal direction of surface of substrate 1, a drain electrode 9d and source electrode 9 s of one electrode (here is source electrode 9 s) on the metal oxide layer 7 has a recess, and the other electrode (here is the drain electrode 9d) arranged at spaced intervals in the source electrode 9 s with the source electrode 9 s. Therefore, the channel region of the source electrode 9 s and the drain electrode 9d and 7c has a U shape. Under this condition, as shown in FIG. 1 (b), is located between the source electrode 9 s and the drain electrode 9d of the width of the gap portion is the groove length (channel direction length) L1. the length of the line from the addition, channel region of source electrode 7c 9 s and the distance from the drain electrode 9d is equal to the distance, in other words, the length of the line source electrode 9 s connected with the drain electrode 9d on the metal oxide layer 7 on the separation distance of the two quartering points, is a channel width (length in the direction orthogonal to the channel direction) W1. In addition, memory transistor 10 of channel region 7c (in plan view) shape and is not limited to U-shaped and can be rectangular for example.
storing structure of transistor 10A is not limited to the bottom-gate structure, also can be the metal oxide layer 7 above the gate electrode 3 of the top gate structure. no matter the memory transistor 10A with which one of the above structures under the condition, only configured when viewed from the normal direction of the substrate 1, and the second drain electrode metal layer 9d2 not overlapped with the gate electrode 3 and the metal oxide layer 7 both overlap, it can obtain the effect of the present invention.
a first drain metal layer 9d1 may be layer 7 is in direct contact with the metal oxide. Thus, it is possible to reduce the first drain metal layer 9d1 and the contact resistance of the metal oxide layer 7. the first drain electrode metal layer 9d1 may contact with the upper surface of the metal oxide layer 7 (top contact) structure, also can be contacted with the lower surface of the metal oxide layer 7 (bottom contact structure).
a first drain metal layer 9d1 (first metal film 9 L) and the second drain metal layer 9d2 (second metal film 9U) stack order is not particularly important. In the example shown in FIG. 1, the first drain electrode metal layer 9d1 is configured on the second drain metal layer 9d2 of the substrate 1 to one side, but can also be configured at the opposite side of the substrate 1. for example, FIG. 36 (a) in the example described, the source electrode 9 s and the drain electrode 9d can also have a second source electrode metal layer 9s2 and the second drain metal layer 9d2 as the lower layer, first source electrode metal layer 9s1 or the first drain electrode metal layer 9d1 (the first metal film 9 L) is laminated structure of the upper layer. In addition, when the first metal film 9 L the arrangement position of the metal oxide layer 7 to be closer than the second metal film 9U side can utilize the first metal film 9 L (a first drain metal layer 9d1 and the first source metal layer 9s1) prevents the second metal (in particular Al, Cu), a second metal film 9U (second drain electrode metal layer 9d2 and the second source metal layer 9s2) is diffused into the metal oxide layer 7.
The semiconductor device of the embodiment may include a plurality of memory transistors 10A. Preferably, a plurality of memory transistors 10A are provided with the electrode structure. In this case, after the writing action of the semiconductor device comprises: a semiconductor state of the memory transistor (storage transistor ST) and the resistive state of the memory transistor (memory transistor RT). In the storage transistor RT to form drain electrode 9d of metal by writing the heat melting, the result can suppress source-metal oxide layer-drain current path is broken and damaged. Moreover, for example, only by observation from the normal direction of the substrate 1, storage transistor ST, RT is not easy to distinguish, so the safety is improved.
a metal oxide layer 7 containing a metal oxide such as containing In, Ga and Zn oxide. a metal oxide layer 7 can be made of a film of an In-Ga-Zn-O based semiconductor. In addition, the In-Ga-Zn-O based semiconductor is In (indium), Ga (gallium), ratio (component ratio) is not particularly limited ternary oxide, In, Ga and Zn, Zn (zinc), including, for example, In: Ga: Zn=2: 2: 1, In: Ga: Zn=1: 1: 1, In: Ga: Zn=1: 1: 2. metal oxide layer of this exemplary embodiment 7 may be, for example, In: Ga: Zn=1: 1: 1 with the ratio of In, Ga, Zn, Ga-Zn-based metal oxide layer. In addition, the metal oxide layer of the memory transistor ST before writing of 7 semiconductor layer, but after writing of the memory transistor RT in at least the channel region of the metal oxide layer 7 does not exhibit semiconductor characteristics.
under the condition of using In-Ga-Zn-O based semiconductor film that can form a storage transistor 10A and memory transistor 10A formed using a common semiconductor film other transistor (oxide semiconductor TFT) on the same substrate, is advantageous. thus the oxide semiconductor TFT with a TFT of high mobility (more than 20 times) and a low leakage current (a-Si TFT) of less than 1/100). so it can greatly reduce the power consumption of the semiconductor device.
In-Ga-Zn-O based semiconductor may be amorphous, may also comprise the crystalline portion. as crystalline In-Ga-Zn-O based semiconductor, can be oriented using a c-axis is substantially perpendicular to the plane of crystalline In-Ga-Zn-O based semiconductor. crystal structure of the In-Ga-Zn-O based semiconductor such as has been disclosed Japanese Publication 2012-134475 gazette. For the purpose of reference, the instruction invoking all disclosed contents of Japanese special 2012-134475 number gazette.
the other semiconductor film can also replace an In-Ga-Zn-O based semiconductor is used due to joule heat and low resistance. For example, it can use content of NiO, SnO2, TiO2, VO2, In2O3, SrTiO3 of the semiconductor film. or, it also can use Zn-O based semiconductor (ZnO), In-Zn-O based semiconductor (IZO (registered trademark)), Zn-Ti-O based semiconductor (ZTO), Cd-Ge-O-based semiconductor. Cd-Pb-O based semiconductor, CdO (cadmium oxide), Mg-Zn-O based semiconductor, In-Sn-Zn-O based semiconductor (such as In2O3-SnO2-ZnO), In-Ga-Sn-O-based semiconductor. Furthermore, it also can be used in the oxide semiconductor film added with various impurities.
less than storing the action of transistor 10A
As for the memory transistor 10A, as for example by the semiconductor state (initial state) is assigned to logic value "0", and the states are assigned to logic value "1", it can be used as non-volatile memory information storage circuit. the following, one example of the structure and an action of the memory circuit using the memory transistor 10A will be described. storage circuit comprises 1 or more memory cells.
FIG. 2 is a example of a single storage unit storage circuit. storage unit such as a memory transistor 10A and a storage unit 10A are connected in series with the memory transistor select transistor (called "selection transistor") for 10a. storage circuit with, for example, by arranging a plurality of memory cell matrix structure.
the selection transistors 10a of the structure is not particularly limited, but, may have with the storage transistor 10A of metal oxide layer 7 from the oxide semiconductor film to form an active layer. Therefore, it can be convenient to manufacture the memory transistor 10A and the selection transistor 10a by a common procedure.
in the storage unit shown in FIG. 2, so as to form the conduction state by applying a gate voltage selection transistor 10a, the storage transistor 10A for writing or reading operation.
a memory writing can of transistor 10A by applying a predetermined gate electrode of the memory transistor 10A in a period (writing time) Tpp of the gate voltage Vg, and the drain electrode by applying a predetermined write voltage Vpp. the period, source electrode of the selecting transistor 10a is connected to the fixed voltage (e.g., ground potential). Thus, the memory transistor 10A in the period Tpp, the channel region has a write current Ipp to flow. under the action of the writing current Ipp caused by Joule heat to form an oxide semiconductor channel region of the chemical component ratio is changed, a channel region to form a resistor body state after low resistance.
storing the read transistor 10A can be carried out by the following method, namely, to the current (read current) for applying a predetermined voltage between the source-drain of the memory transistor 10A to flow the gate voltage dependency to investigate. Specifically, in semiconductor state of flow of the read current in the memory transistor 10A is multiplied, it is possible to easily judge based on a ratio of the read current Ir and the current reading. In addition, if the gate voltage Vgs during reading is set within a predetermined voltage range (e.g., about 0.5V degrees), then because the read current difference with the read current Ir, can more easily identify the memory state of transistor 10A.
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Here, preparation embodiment and reference example of the memory transistor 10 (1), 10 (2), comparison by writing the memory transistor caused by damage.
In FIG. 3, (a) and (b) are respectively a sectional view and a plan view of the memory transistor of the embodiment 10 (1). storage transistor 10 (1) and shown in FIG. 1 the difference of the memory transistor 10A, a source electrode 9 s in part Q of the metal oxide layer 7 is composed of only the first source metal layer 9s1 and the second source metal layer 9s2 is disposed on the metal oxide layer 7. the other structure and the memory transistor 10A are the same. the memory transistor 10 (1), as the first drain electrode metal layer 9d1 and the first source metal layer 9s1 forming a Ti layer as the second drain electrode metal layer 9d2 and the second source metal layer 9s2 forming an Al layer, Ga-Zn-based semiconductor layer is formed as the metal oxide layer 7. In addition, the memory transistor 10 (1) of the channel length L is, for example, not less than 1um and not more than 20um, the channel width is more than 2um and less than 1 mm, thickness of the metal oxide layer 7 is not less than 5nm and not more than 500nm.
preparing memory transistor 10 (2) as a reference example, which has existing bottom gate-top contact type TFT has a laminated structure using the source electrode and the drain electrode of the transistor structure.
In FIG. 4, (a) and (b) are respectively a sectional view and a plan view of the memory transistor of the reference example 10 (2). memory transistor 10 (2) only in the second source metal layer 9s2 and the second drain metal layer 9d2 on the metal oxide layer 7 is also configured with the storage transistor 10 (1). That is, the memory transistor 10 (2), the drain electrode 9d part P comprising a second drain metal layer formed by metal with low melting point of 9d2. other structure, material and thickness of each layer and the memory transistor 10 (1) are the same.
the memory transistor 10 (1) and 10 (2) to perform a write-in operation under the same condition to observe each transistor after writing. Here, as the write condition, the write voltage Vds is 50V, the gate voltage Vgs is 40V, writing time is 100msec.
FIG. 3 (c) is a representation of a memory transistor after writing 10 (1) view, and FIG. 4 (c) is a view of after writing of the memory transistor 10 (2). can be confirmed, the storage transistor of reference example 10 (2), the metal oxide layer 7 is formed on the puncture marks D according to FIG. 4 (c). breakdown trace D can be taken as the drain electrode 9d of the channel end part of one side of break due to metal melting trace. is subjected to a reading operation of the memory transistor after writing 10 (2), but can not flow current between the source and the drain, and is hard to read for measuring current. opposite to each other in the embodiment, according to FIG. 3 (c), it does not see the deformation and breakdown of the drain electrode 9d trace, reading operation can be normally performed. It can be seen from this, according to the present embodiment can suppress heat generated by writing that the memory transistor is broken down.
less than a semiconductor device structure
The embodiment can be widely applied to the electronic device comprising a storage circuit. The semiconductor device of the embodiment as long as it has at least one memory transistor 10A, its use and the structure is not limited. for example, may be a non-volatile semiconductor memory device, an integrated circuit (IC, LSI) active matrix substrate in the liquid crystal display device or an organic EL display device and other display device, each display device used.
the semiconductor device further comprising a thin film transistor, the thin film transistor having an active layer formed of an oxide semiconductor film 10A with the storage transistor active layer (metal oxide layer 7). thin film transistor can be formed circuit elements.
in the application under the condition of display device of active matrix substrate in this embodiment can be the active display area of the matrix substrate other than a region (peripheral region) setting includes memory transistor 10A of the memory circuit. a peripheral region, can be used as circuit elements constituting the drive circuit and other peripheral circuit thin film transistor is formed (circuit transistor). In addition, it also can form a thin film transistor as a switching element provided in each pixel of the display region (pixel transistor). circuit can have an active layer formed of an oxide semiconductor film and the active layer of the memory transistor 10A, and the source electrode of the memory transistor 10A, and the drain electrode shared by stacking a conductive film forming the source electrode and the drain electrode for the transistor with transistor and pixel. circuit can have the same transistor structure storage transistor 10A transistor transistor and a pixel. In this case, these transistors can be connected to storage transistor 10A by a common process. However, because the circuit does not write transistor is used for transistor and pixel, so the drain electrode when it is observed from normal direction of substrate in the active layer and the gate electrode overlap portion can also contain lower melting point metal or alloy.
below with reference to the accompanying drawings will be described more detailed structure of the semiconductor device of this exemplary embodiment.
less active structure of the matrix substrate
The embodiment can be applied to an active matrix substrate such as used in the liquid crystal display device.
FIG. 5 (a) shows a part of the active matrix substrate 1002 a plan view. an active matrix substrate 1002 having a plurality of pixels 101 of the display region 100 and the display region other than the region (peripheral region) 200.
the display 100 of each pixel area 101 as a switching element is formed with a thin film transistor (referred to as "pixel transistor") 10T. pixel-used transistor 10T may have with the storage transistor 10A (FIG. 1) is the same as that of the transistor structure. In addition, as shown in FIG. 5 (b) shows an example of the above, in the drain electrode 9d and the metal oxide layer 7 and a gate electrode 3 overlapped portion may form a second drain metal layer 9d2.
at the periphery area 200, at least a portion of the plurality of circuit (storage circuit) such as display device and a drive circuit is formed in a monolithic circuit, although not shown. the formed in the periphery circuit region 200 is called "peripheral circuit". In this embodiment, the memory transistor 10A is, for example, formed in a peripheral region 200 of a memory circuit.
Each pixel 101 is provided with extending along the column direction of the pixel of the source lines S, gate wiring G and the pixel electrode extending in a row direction of the pixel 19. pixel-used transistor 10T is configured in the source lines S and the gate wiring G near the crossing point. In the example shown, pixel 101 is provided are formed by the same conductive film and gate wiring G of the capacitor line CS. capacitor line CS is a capacitance part 20 is configured.
In this embodiment, source wire S, the pixel transistor 10T and the storage transistor 10A of the source and drain electrodes are formed in the same wiring (source wiring layer). a source electrode wiring layer may have a laminated structure containing, for example, a high melting point metal formed first metal film 9 L (FIG. 1) and lower than the second metal film is formed of a metal having a melting point of 9U (FIG. 1).
the peripheral region 200 is provided with a plurality of gate wire G or the source wiring S connected with the external wiring of the terminal portion 201. source wiring S extends to the end of the display region 100, and the source electrode connecting part 9sg. the source electrode connecting part 9sg connecting part 3sg electrically connected with the gate, the gate connection part 3sg is formed by the same film with the gate wiring G. the connecting part is called " source grid connected part 30. gate connection part 3sg is extended to the peripheral region 200 through the terminal (source terminal) 201 with, for example, the source driver (not shown). On the other hand, gate wiring G also extends to the peripheral area 200, through terminal (gate terminal) and, for example, a gate driver (not shown) is connected, not shown and not shown.
the peripheral region 200 includes a plurality of peripheral circuit (not shown) is formed as a monolithic circuit storage circuit. For example, may be formed with a gate driver, a source driver and drive circuit, and memory circuit connected with each driving circuit. storage circuitry comprises a memory transistor 10A shown in FIG. 1.
Active matrix substrate 1002 can be applied to a liquid crystal display device and other display devices. liquid crystal display device such as shown in FIG. 5 (c), comprising: an active matrix substrate 1002, surface has an opposing electrode 42 of the opposite substrate 41, and a liquid crystal layer arranged between them 43. using the pixel electrode 19 and the counter electrode 42 of the liquid crystal layer 43 for each pixel voltage applied so as to display.
FIG. 6 is an example that uses the active matrix substrate 1002 of the liquid crystal display device 2001 of the module structure of FIG. In FIG. 7, (a) and (b) is a schematic diagram of the structure of a pixel circuit composing storage unit and liquid crystal display devices 60a to 60c of the nonvolatile storage device 2001.
the liquid crystal display device 2001 includes a display unit having a plurality of pixels 71. display part 71 and the display region 100 of the active matrix substrate 1002 (FIG. 5 (a)). In this embodiment, display portion 71 is disposed in matrix with a plurality of pixel circuits 70. the pixel circuits 70 through the source line SL1 to SLk, the gate lines GL1 to GLj and auxiliary capacitance lines CSL1 to CSLj are connected to each other.
as shown in FIG. 7 (b), each pixel circuit 70 has a pixel transistor 10T, a liquid crystal capacitance Clc and the auxiliary capacitance Cs. the source electrode of the pixel-used transistor 10T connected with the source lines S, gate electrode connected with the gate line G, the drain electrode and the pixel electrode (not shown). liquid crystal capacitance Clc is formed by the pixel electrode and the common electrode COM and the auxiliary capacitor Cs is formed by the pixel electrode and the capacitor line CS.
the liquid crystal display device 2001 further comprises a source electrode driver electrically connected 75 with the source wiring S, gate driver to the gate wiring G electrically connected 76, electrically connected to the capacitor line CS of the CS driver 77 and a common electrode drive circuit for driving the common electrode 74. the driving circuits 75, 76, 77, 74, and the display control circuit 73 and a power supply circuit (not shown) is connected, wherein the display control circuit 73 for controlling the timing and the source wiring S, gate wire G, the capacitor line CS and the common electrode voltage applied to these circuits for supplying power In addition, the source driver 75, the gate driver 76 and the display control circuit 73 are respectively connected with the non-volatile memory device 60a, 60b, 60c. 60a, a nonvolatile memory device 60b, 60c and the shared memory control circuit part 61 is connected.
non-volatile storage device 60a, 60b, 60c having, for example, a plurality of memory cell arrays formed by arranging structure. memory cell includes a storage transistor 10A. storage unit may have a structure of already described referring to FIG. 2. or may be shown as an example in FIG. 7 (a), instead of selection transistors 10a shown in FIG. 2, connected in parallel with 2 or more than 2 of the selection transistors 10a, 10b.
non-volatile storage device 60a is stored in the structure information of the display panel, the unique ID and so on. These stored in non-volatile storage device 60a in the information by the display control circuit 73 refers to based on the information for switching the display control method in detail, or for the optimization of control parameters. In addition, the unique ID from a system such as a side panel is connected to the display to search, which is used for judging the display panel and selection of optimal driving method. display control circuit 73 based on the information stored in the non-volatile storage device 60a in the switching information for performing display control of the circuit to achieve the best display control of the display panel.
non-volatile storage device 60b stored in a gate driver of redundancy repair (redundancyrelief) information and the like of the gate driver driving the necessary structure information of the parameter. Similarly, the nonvolatile storage device 60c stores necessary for driving of the redundancy rescue information such as source electrode driver of a source driver of the structure information of the parameter.
at least a portion of a nonvolatile memory device 60a, 60b, 60c and a circuit outside the display section 71, 73, 74, 75, 76, 77, 61 at least a portion of the peripheral region 200 of the active matrix substrate 1002 (FIG. 5 (a)) is formed as a monolithic circuit. In this embodiment, for example, the gate driver 76 formed on the active matrix substrate is a monolithic circuit.
Next, the manufacturing method of the active matrix substrate 1002 of one example will be described with reference to the accompanying drawings.
FIG. 8 to FIG. 13 is used to explain the manufacturing method of the active matrix substrate 1002 of the process graph, each graph of (a) and (b) is a sectional view, (c) is a plan view. the accompanying drawings respectively showing an active matrix substrate 1002 for forming a memory transistor 10A, 10B in the region R (10A) and R (10B), R region (20) forming the capacitor part 20, forming a gate region of the source contact part 30 R (30) and forming a gate source cross part 40 of the region R (40). part of the conducting layer crossing the conductive layer on the gate source cross part 40 refers to the gate wiring or formed by the same conductive film and gate wiring via an insulating layer and source electrode wiring or formed by the same conductive film and the source wiring. In addition, in the drawings, for the sake of convenient, the memory transistors 10A, 10B and capacitor 20 forming area are represented, but the configuration of forming region thereof, and are not limited to the illustrated configuration. Furthermore, the semiconductor device 1002 does not necessarily includes the 2 memory transistors 10A, 10B, as long as it has any one of memory transistors.
firstly, using, for example, sputtering for forming a gate conductive film on the substrate 1, and using a known dry etching patterning it. Therefore, as shown in FIG. 8 (a) to FIG. 8 (c), the gate source contact part forming region R (30) forming a gate connecting portion 3sg, region R is formed the gate source cross part (40) forming a gate wiring G and the memory transistor forming region R (10A) forming a gate electrode 3A, the capacitor part forming region R (20) form a capacitor line CS, the memory transistor forming region R (10B) forming a gate electrode 3B. using the grid formed by conductive film comprising these wiring and electrode layer is called " gate wiring layer.
As a substrate 1, capable of using a transparent insulating substrate such as a glass substrate, for example. as the gate conductive film, such as aluminum (Al) is used, a single layer film of chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo) or tungsten (W), which are more than 2 layers of the laminated film, or 2 by element of at least one kind of the metal elements in the composition of the alloy film. for example, can use a Ti film, Al film and Ti film of 3 film (Al/Ti) from one side of the substrate 1, or a Mo film, an Al film and Mo film of 3 film (AL/). In this embodiment, as an example, from the substrate 1 using Al film and thickness has a Ti film whose thickness is 10 to 100nm, thickness is 50 ~ 500nm is 50 ~ 300nm of the Ti film 3 film (Al/Ti).
then, forming a gate insulating film 5 in a manner covering the gate wiring layer. a gate insulating film 5 is, for example, formed by plasma CVD method, sputtering method and so on. a gate insulating film 5, for example, can be selected from silicon oxide film (SiO2) and a silicon nitride film (SiN), a silicon oxynitride film (SiON), silicon oxynitride film (SiON), alumina (Al2O3) and single-layer tantalum oxide (Ta2O5) or more than 2 layers of laminated film. In this embodiment, as one example, using the substrate 1 a side in turn with 2 film SiO2 film has a thickness of 100 to 500nm nm of SiN film whose thickness is 20 to 100nm.
Next, the gate insulating film 5 is, for example, formed by sputtering the oxide semiconductor film (thickness: e.g., 5 to 500nm), then patterned by known wet etching for the oxide semiconductor film. Therefore, as shown in FIG. 9 (a) to FIG. 9 (c), in the memory transistor formation region R (10A) form a metal oxide layer 7A, the memory transistor forming region R (10B) forming metal oxide layer 7B. a metal oxide layer 7A, 7B each via a gate insulating film 5 in a manner of corresponding to the gate electrodes 3A, 3B are overlapped. Here, the gate electrode width of 3A, 3B the channel direction are substantially the same, and the channel direction of the metal oxide layer 7A having a width less than width of metal oxide layer 7B the channel direction. For example, as shown, the metal oxide layer 7A the channel direction width is less than width of gate electrode 3A the channel direction, and the metal oxide layer 7B the channel direction is wider than the width of gate electrode 3B the channel direction. parasitic capacitance by using this structure, it can differentiate the manufacturing channel length different transistor structures, and will not increase the gate electrodes 3A, 3B and the source/drain electrode overlapping part.
as the oxide semiconductor film, for example, can use the oxide semiconductor film containing In, Ga, and Zn. In this embodiment, using the In-Ga-Zn-O based amorphous oxide semiconductor film (thickness: e.g., 5 to 500nm). the semiconductor film is an n-type metal oxide semiconductor, formed under low temperature. component of each metal element is In-Ga-Zn-O based oxide semiconductor film in the ratio of In: Ga: Zn is 1: 1: 1. even if the component ratio of the reference adjusting component ratio, it can exert the effect of the invention.
Next, as shown in FIG. 10 (a) to (c), the gate insulating film 5 and the metal oxide layer 7A, 7B, as the source for conductive film 9 formed in the first metal film 9 L as the lower layer, the second metal film 9U is a laminated film of the upper layer, after the patterning for the first time.
the first metal film 9 L is a metal (including alloy) with a high melting point metal film. In addition, it can be a high melting point metal nitride and metal compound film. the first metal film 9 L, for example, can be metal film of W, Ta, Ti, Mo, Cr, and so on. a second metal film 9U is a metal (including alloy) with low melting point is formed of the metal film. In addition, it can be lower a melting point of metal nitride and metal compound film. the second metal film 9U can be, for example, Cu, Al and the like, a metal film. 2 layer structure source may, for example, have 2 layer structure with Ti film as lower layer, an Al film as the upper layer of the Ti film Al film and the Mo film as lower layer, an Al film as the upper conductive film of Mo film film used, or contains more than 3 layers of the laminated structure of the 2 layer. Here, for example, by sputtering continuously as the first metal film 9 L to form a Ti film (thickness: 10 to 100nm), forming an Al film as the second metal film 9U (thickness: 50 to 400nm).
for a source electrode of the first metal film 9 L and second metal film 9U with a conductive film 9, for example, using wet etching for patterning for the first time. wet etching only the second metal film 9U is etched without etching the first metal film 9 L is carried out. Thus, in the second metal film 9U of the memory transistor 10A, 10B of the metal oxide layer 7A, 7B on the part respectively form an opening. the first metal film 9 L exposed in the opening. each opening portion comprises a set of metal oxide layers 7A, 7B formed in a whole area of the drain contact region and a partial region of the channel region.
Then, as shown in FIG. 11 (a) to (c), the source for the conductive film 9 is formed into a resist layer having an opening in the area of the channel region of the memory transistor 10A, 10B. Thereafter, using a resist layer M is the source electrode conductive film for the patterning for the second time. the second patterning, such as resist layer as mask, using wet etching to remove the second metal film 9U, and then removed by dry etching the first metal film 9 L. Thus, removing the first and second metal films 9 L, 9U of 7A, 7B of the metal oxide layer in the region to be the channel region on the part (the source-drain separation).
Thus, the memory transistor forming region R (10A) and R (10B) form the source electrodes 9sA, 9sB and drain electrodes 9dA, 9dB. and the gate electrode contact part forming region R (30) forming the source electrode connecting part 9sg, the gate source cross part forming region R (40) forms a source wiring S, the capacitor part forming region R (20) forms a capacitor electrode 9cs. the formed using source conductive film comprising these wiring and electrode layer referred to as a source wiring layer. source electrodes 9sA, 9sB are composed of the first metal film 9 L formed by the first source metal layer 9s1A, 9s1B is lower in a laminated electrode (or a lamination wiring) formed by the second metal film 9U the second source metal layer 9s2A, 9s2B is the upper layer. Similarly, the drain electrodes 9dA, 9sB are composed of the first metal film 9 L formed by the first drain metal layer 9d1A, 9d1B is lower in a laminated electrode (or a lamination wiring) formed by the second metal film 9U the second drain metal layer 9d2A, 9d2B is the upper layer.
Here, the second metal film 9U is patterned by wet etching, therefore, in the source wiring layer, when viewed from the normal direction of the substrate 1. The end placed on the second metal film 9U than the end of the resist layer M is more closer to the inner side. and the first metal film 9 L by the dry etching for patterning, so when viewed from the normal direction of the substrate 1, the first metal film 9 L and the resist layer M end substantially matching. in the profile so that, when viewed in a normal direction of the substrate 1 source wiring layer, and the second metal film 9U located on the first metal film 9 L. In the sectional view, the end of the second metal film 9U located on the first metal film 9 L. Furthermore, because the first patterning to form area of the drain contact region of the second metal film 9U is removed, so the metal oxide layers 7A, 7B of the drain contact region is only remained with a first metal film 9 L.
a source electrode 9sA and a drain electrode 9dA is configured electrically separated from each other, and are each in contact with a portion of the metal oxide layer 7A. Similarly, the source electrode 9sB and the drain electrode 9dB is configured electrically separated from each other, and are each in contact with a portion of the metal oxide layer 7B. when viewed from the normal direction of the substrate 1, a metal oxide layer 7A, 7B and 3A, 3B overlap the corresponding gate electrode, and located between the source electrodes 9sA and 7sB and drain electrodes 9dA, 7dB between the region to be a channel region 7cA, 7cB. In this embodiment, for example, the memory transistor forming region R (10A) such that the channel region 7cA when viewed from the normal direction of the substrate 1 in U-shaped manner, configuring the source electrode 9sA and the drain electrode 9dA. On the other hand, the memory transistor forming region R (10B) such that the channel region 7cB when viewed from the normal direction of the substrate 1 is rectangular configured in the way the source electrode 9sB and the drain electrode 9dB.
so as to form the memory transistor 10A, 10B. is only composed of the first metal film 9 L is overlapped with the metal oxide layer 7A, 7B and the gate electrodes 3A, 3B the two parts of any one of transistors 10A and 10B, drain electrodes 9dA, 9dB, does not include the second metal film 9U. On the other hand, the source electrodes 9sA, 9sB are overlapped with the metal oxide layer 7A, 7B and the gate electrodes 3A, 3B the two part includes the first metal film 9 L and second metal film 9U.
and, the capacitor forming region R (20) form a capacitor line CS, a capacitor electrode 9cs and a capacitor part of the dielectric layer (the gate insulating film 5) located 20 between them. the gate source cross part forming region R (40) formed by the gate wiring G and source wiring S via a gate insulating film 5 the gate source cross part cross 40. the gate electrode contact region R is formed (30), source electrode connecting part 9sg with sandwiching the gate insulating film 5 and the gate connection part 3sg a partially overlapping manner.
In addition, although not shown, pixel transistor 10T (refer to FIG. 5 (a), (b)) and a circuit can also to memory transistor 10A, 10B by a common process for forming transistors. the pixel transistor 10T and the circuit in the transistor, as shown in FIG. 5 (b) example described, drain electrode of the second metal film 9U may be disposed on the metal oxide layer 7.
Next, as shown in FIG. 12 (a) to FIG. 12 (c) by, for example, by using plasma CVD method or sputtering method so as to cover the source wiring layer forming a protective film (passivation film) 11. as the protective film 11, for example, it can use selected from silicon oxide film (SiO2) and a silicon nitride film (SiN), a silicon oxynitride film (SiON), silicon oxynitride film (SiON), alumina (Al2O3) and single-layer tantalum oxide (Ta2O5) or more than 2 layers of laminated film. In this embodiment, as one example, as the protection film 11 using the CVD method to form the SiO2 film (thickness: e.g., 50 to 500nm).
Then, annealing is done for 30 minutes to about 4 hours in an air atmosphere at a temperature of 200 to 400 ℃. Therefore, the reaction layer is formed on the metal oxide layer 7A, 7B the interface between the source 9sA, 9sB and drain electrodes 9dA, 9dB. Therefore, it is possible to reduce the source electrodes 9sA, 9sB and drain electrodes 9dA, 9dB and the contact resistance of the metal oxide layer 7A, 7B.
Then, as shown in FIG. 13 (a) to (c), can according to the need of forming a planarized film on the passivation film 11. In this embodiment, forming a photosensitive resin, for example, as a planarization film such as an organic insulating film 13. performing patterning on the organic insulating film 13 using well-known photolithography (exposure, development, drying). Accordingly, a region R (30) is the gate source contact portion on the organic insulating film 13 is formed by part of the opening part. Then, the organic insulating film 13 as a mask, the gate insulating film 5 and the passivation film 11 is etched. In the etching, the source electrode connecting part 9sg and the gate connecting portion 3sg as an etch barrier layer. Thus, the gate insulating film 5 is formed by the source electrode connecting part 9sg covers the parts which are not etched but remained. Also, it is possible to make the gate connecting portion 3sg and source connecting part 9sg exposed to the surface of the contact hole 15.
then, forming a conductive film on the organic insulating film 13 and in the contact hole 15, and patterned. Therefore, when the gate source contact portion formation region R (30) obtained in the contact hole 15 the gate connecting portion 3sg and source connecting part 9sg electrically connected to the upper conductive layer 17. so as to form the gate electrode contact portion 30.
In this embodiment, as the conductive film using ITO film (thickness: e.g., about 20nm to 300nm) such as a transparent conductive film. In addition, it can use the conductive film according to each pixel forming the pixel electrode 19 is formed (FIG. 5 (a)). so as to obtain the active matrix substrate 1002.
The semiconductor device of the embodiment is not limited to an active matrix substrate 1002 or display device using the substrate. This embodiment can be suitably applied to an oxide semiconductor TFT and device non-volatile memory. For example, the memory transistor 10A can be at a relatively low temperature (e.g., less than 200 ℃) under manufacturing, so it can be applied to an IC tag and the like. In this case, the memory transistor 10A can be used for ID storage. In addition, because can use transparent metal oxide film as the oxide semiconductor film, so it can be used for mass storage device for digital signage. except the storage device, also can be applied to ASIC (ApplicationSpecificIntegratedCircuit, an application-specific integrated circuit), FPGA (Field-ProgrammableGateArray, field-programmable gate array) programmable logic circuit device.
less storage electric characteristics of transistor 10A
Here, referring to FIG. 14 to FIG. 20 illustrate the electrical characteristics of the storage transistor 10A.
as the memory transistor 10A, preparing Ga-Zn-based oxide semiconductor is used as the metal oxide layer 7 of the n-channel thin film transistor, measuring electrical properties written before and after writing. L1 is 10A microns in the assay using the channel length of the memory transistor 4, the channel width W1 is 20 um, the thickness 7A of the active layer (metal oxide layer) is 20 to 100nm, the channel region 7cA of a planar shape of a rectangle or U shape.
memory transistor 10A immediately after production (initial state) exhibit the usual thin film transistor the same transistor characteristics. each of the drain current Ids (flow from the drain electrode to the source electrode of the current) depending on the gate voltage Vgs (based on the source electrode voltage applied on the gate electrode) and the drain voltage Vds (based on the source electrode voltage) applied to the drain electrode to change.
FIG. 14 (a) represents an initial state of the memory transistor 10A, Ids-Vgs characteristic of Vds=0.1V and Vds=10V under the condition of FIG. FIG. 14 (b) represents an initial state of the memory transistor 10A, the Vgs from 0V to 7V according to the Ids-Vds characteristic of each 1V change in FIG. wherein the bitmap value of drain current Ids 14 (a) and (b) is represented by per unit gate width (1 microns) and the drain current (unit drain current) value.
According to FIG. 14 (a) and (b), clearly, for the memory transistor in the initial state 10A, the gate voltage Vgs is about less than 0.5V nm (specific voltage range), the drain voltage Vds is in the range of more than 0.1V and less than 10V, the unit drain current is very small (e.g., 1 * 10-14A/ [mu] m or less). This actually is in closing state. When the gate voltage Vgs is larger than the specific voltage range, as the increased gate voltage Vgs, the drain current Ids is increased (FIG. 14 (a)). Moreover, along with the increase in drain voltage Vds, the drain current Ids is increased (FIG. 14 (b)).
the memory transistor of this initial state (also called semiconductor state) 10A to perform a write-in operation, the electric characteristic investigation after writing. writing is done like this, namely, the memory transistor 10A the gate voltage Vgs and the drain voltage Vds is applied, so that the channel region 7cA has a large drain current flows. Because of the drain current, the metal oxide layer 7A is locally generating Joule heat can make the resistance of the channel region 7cA is reduced. In addition, the gate voltage Vgs is written by circuit action such as setting ratio range for applying the circuit high voltage of the gate voltage on the transistor. Here, the memory transistor 10A with drain voltage Vds is 24V and the gate voltage Vgs 30V for writing. writing time (the electrifying time of drain current Ids) is 100 m seconds.
FIG. 15 (a) represents the storage write-in action of transistor 10A, Ids-Vgs characteristic of Vds=0.1V and Vds=10V under the condition of FIG. FIG. 15 (b) shows after the memory write operation, the Vgs of transistor 10A from 0V to 7V according to the Ids-Vds characteristic of each 1V change in FIG.
In addition, as shown in FIG. 16, in order to compare the electrical characteristics and before writing the write before (initial state) and after writing memory transistor 10A under the condition of Vgs=0V near the origin of the Ids-Vds characteristic of the amplified image. line R1 represents the Ids-Vds characteristics before writing, line T1 represents the Ids-Vds characteristic after writing.
FIG. 17 is a 10A Ids-Vgs characteristic of the memory transistor and before writing the overlay representation. lines T2 and T3 respectively represent the Vds of the Ids-Vgs characteristic of the write 0.1V and 10V front. Ids-Vgs characteristic lines R2 and R3 respectively represent a Vds is written in 0.1V and 10V.
FIG. 18 is a 10A according to the Ids-Vds characteristic of the memory transistor and before writing the obtained differential resistance (dVds/dIds, unit: Omega mu m) and the drain voltage Vds of the relationship of FIG. line T4, T5 respectively represent the gate voltage Vgs is the relationship of dVds/dIds and Vds before written in 0V and 7V. line R4, R5 respectively represent the gate voltage Vgs is the relationship of dVds/dIds and Vds is written in 0V and 7V.
According to FIG. 15 (a) and (b), clearly, after writing of the memory transistor 10A, the drain current Ids is substantially dependent on the gate voltage Vgs, which is mainly dependent on the drain voltage Vds. if the drain voltage Vds, the drain current Ids is approximately a fixed value. In addition, the IV curve and the gate voltage Vgs-Ids-Vds characteristic of the gate voltage Vgs is approximately linear, and is through the origin (Ids=0A/, Vds=0V). That is, it is possible to know the memory transistor after writing 10A is ohmic resistance characteristic of the resistor. the original point of the differential resistance (dVds/dIds) is neither is infinite or finite value is not 0.
a storage transistor in the initial state 10A, if the drain voltage Vds, the drain current Ids depending on the gate voltage Vgs. and under the gate voltage Vgs is within a certain voltage range (e.g., about 0.5V or less), the drain current Ids substantially does not flow is substantially off state. oppositely, after writing, if the drain voltage Vds, regardless of the gate voltage Vgs, the drain current Ids flows. under the gate voltage Vgs in the case specific voltage range, the above range of less than 10V if the drain voltage is, for example, 0.1V, then the unit drain current is 1 * 10-11A/ [mu] m or more.
Thus, for the memory transistor 10A, the semiconductor state, the absolute value of the drain voltage is in the range of not less than 0.1V and not more than 10V, the drain current Ids/W1 of the absolute value of grid voltage exists so the unit channel width is a voltage range of the small current state such as 1 * 10-14A/ [mu] m or less. after the change is a resistive state, the absolute value of the drain voltage is in the range of not less than 0.1V and not more than 10V, even when the gate voltage is set as the voltage range, the unit channel width of the drain current absolute value of Ids/W1 also can be the drain voltage to become for example 1 * 10-11A/ [mu] m or more current state.
In addition, according to FIG. 18 can be known, the differential resistance dVds/dIds at initial state varies with gate voltage Vgs. and the differential resistance dVds/dIds after writing is not varies with gate voltage Vgs.
Next, the memory writing operation of transistor 10A further will be described. storing the writing action performed of transistor 10A over the channel region 7cA flows through the high current density in a certain write time of the drain current Ids. high current density of the drain current Ids in the circuit operations other than a write action applied under the bias condition storage voltage range of the gate voltage Vgs and the drain voltage Vds of the transistor 10A on the high flow. by flowing the drain current Ids of the high current density of a predetermined certain write time, generating Joule heat and electromigration in the channel region 7cA. Thus, the components of the metal oxide channel region 7c (metal oxide layer 7) is changed, it may be determined that the low resistance caused thereby. current density (unit: A/m2) In addition, if the thickness of the metal oxide layer 7 a, the unit drain current (unit: um) proportional to the drain current of the relationship. by increasing the unit drain current (unit: um), drain current of current density (unit: A/m2) increases. In this embodiment, the unit of the drain current when the writing operation is, for example, 1/[mu] m to 1mA/ [mu] m, write time is, for example, 10 seconds to 100 seconds. of the gate voltage Vgs is written such as setting is greater than 0V and less than 200V, preferably more than 20V 100V. a drain voltage Vds when writing for example is set below is larger than 0V and less than 200V, preferably more than 20V 100V. However, when writing voltage Vgs, Vds is not limited to the above range, capable of properly set so that a desired unit drain current flow. In addition, the unit drain current and the writing time when a write operation is not limited to the above numerical range. the type and thickness of the metal oxide semiconductor unit drain current and the writing time can be used according to the metal oxide layer 7A, the memory transistor 10A of element structure change.
Joule heat generated in the memory transistor 10A is larger, the electrical characteristics of the storage transistor 10A is easy to change. For example, the unit drain current Ids if increasing the writing, it is possible to generate a larger focal joule.
FIG. 19 shows a writing time (unit: m seconds) the unit drain current (unit: um) relation to one example. The picture 19 we can know, larger Joule unit drain current is larger, more capable of shortening the writing time.
gate voltage Vgs by improving, or of writing unit increases the capacitance of the gate insulating film 5 when writing, it can increase the drain current. However, the gate voltage Vgs is written is set to be lower than the gate insulating film 5 of a dielectric breakdown voltage value. Therefore, gate voltage Vgs in order to further improve the writing, preferably increasing the dielectric breakdown voltage of the gate insulating film 5. From the aspect of this, in this embodiment, the gate insulating film 5 using a material of a high relative dielectric constant to increase the capacitance. as high relative dielectric constant of the insulating material, such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used. their relative dielectric constant than the silicon oxide film (SiO2) and the relative dielectric constant is high. In addition, except the selected material of large dielectric constant, or selection of the large dielectric constant of material at the same time, also can through increasing the thickness of the gate insulating film 5, the gate insulating film is to be applied electric field strength to restrain 5 is low. Thus, it is possible to reduce the dielectric breakdown voltage of the gate insulating film 5. In addition, as the high relative dielectric constant insulating film, if the CVD method to form a silicon nitride film (SiN) and a silicon oxynitride film (SiON), these films will have hydrogen. Therefore, when the SiN or SiON film and contacts as the metal oxide layer of the metal oxide layer 7A, because the oxygen of hydrogen reacts with the oxide semiconductor, the metal oxide layer 7A may close to form the conductor. Therefore, for a metal oxide layer 7A and the silicon nitride film (SiN), a silicon oxynitride film (SiON) can between them so that they do not directly contact manner, inserting the film hydrogen concentration in the silicon oxide film (SiO2) or a silicon nitride oxide film (SiON).
if the memory transistor of the embodiment is easy to generate joule heat structure, or structure of generating Joule heat does not diffuse easily, it is possible to realize higher write characteristic. For example, using the planar shape of the channel region more effectively using the joule heat, which can further shorten the writing time. Specifically, if the plane shape of the channel region such as U shaped, compared with the rectangular can shorten the time required for writing.
FIG. 20 is a diagram of the relation between the plane shape and write time of channel region. the horizontal axis is the gate voltage Vgs and writing voltage Vds (wherein, Vgs = Vds) and the vertical axis is the writing time. the plane shape of the memory transistor and the channel region, the plane shape of the channel is a U-shaped region is rectangular storage transistor to write time. In addition, the channel width and the channel length of the memory transistor is the same, and the plane shape of other than channel region structure (active layer thickness, material and thickness of the gate insulating film) is also the same.
The result shown in FIG. 20, it can be known by making the channel region is U shape, compared with the case of rectangular, can be more efficiently due to the Joule heat generated by the write current used for writing. can be considered the reason thereof is as follows. after forming the U-shaped channel region under the condition when it is observed from normal direction of substrate, formed on at least one of the drain electrode and the source electrode is surrounded by other structure. Therefore, when the surrounding of one part of one side of the electrode, the current density increases, produce larger joule of coke compared with the electrode of the other one side. As a result, low resistance of the oxide semiconductor caused by joule heat is pushed, writing to be promoted. In particular, if the electrode of one of the enclosed is drain electrode, arranged on the outside U-shaped source electrode of the channel region, on the inner side of the U-shaped drain electrode is configured, it is possible to increase a drain-side of the metal oxide layer, so the heat generated can further improve the writing speed. Therefore, if the electrode structure mode of application the memory transistor channel region has a U-shaped, it is possible to obtain more remarkable effect. In addition, the planar shape of the channel region is not limited to the U shape, with the current density locally shape is increased, it can bring the same effect.
less structural example of memory transistor
In order to further increase the writing operation of the memory transistor, the drain current Ids can be opposite in the metal oxide layer 7 and the gate electrode 3 is set on one side of the other gate electrode 18.
FIG. 21 (a) and (b) is an example to illustrate the embodiment of the other memory transistor structure of the plan view and sectional view. In this example, above the metal oxide layer 7 via an interlayer insulating layer (here is a passivation film 11 and an organic insulating film 13) is provided with an upper gate electrode 18. the upper part of gate electrode 18 is configured to, when viewed from the normal direction of the substrate 1, and the metal oxide layer 7 at the channel region 7c overlap. the upper part of gate electrode 18 may be, for example, a transparent electrode formed by a common transparent conductive film and the pixel electrode. Furthermore, an upper gate electrode 18 and the metal oxide layer 7 of the substrate 1 at one side of the gate electrode (gate wiring) 3 can be connected through the contact hole CH. Thus, the further gate electrode 18 and the gate electrode 3 have the same potential, it is possible to further increase the drain current Ids by a back gate effect. like this, the storage transistor is an upper gate electrode 18, there is no need to greatly improve the gate voltage Vgs, which can increase the joule heat, shortening the writing time. In addition, in the example shown in FIG. 21, an upper gate electrode 18 is represented as transparent electrode, but also may not be transparent electrode. In addition, a channel region 7c of a planar shape of a U shape, but may also be rectangular or other shape.
The later described herein, the implementation way of the storage transistor may also have the surface contact to the channel region (7c) is provided with the etch barrier layer etch barrier structure. or may have a metal oxide layer 7 is formed on the source electrode or drain electrode, configured into the bottom contact structure makes the lower surface of the metal oxide layer 7 with the electrode contact.
(second embodiment)
the following explanation the second embodiment of semiconductor device of the invention. points of the semiconductor device of this embodiment and the semiconductor device of the first embodiment, includes a protective layer as the etching barrier layer on the metal oxide layer of the memory transistor. The other structures are the same.
FIG. 22 (a) and (b) shows an example of a plan view and a cross-sectional view 10C of the structure of the memory transistor in the second embodiment. FIG. 22 (b) shows section A-A ' shown in FIG. 22 (a) the section of the line. FIG. 22 to FIG. 1 marked with the same structural elements the same reference numerals and explanations are omitted.
the memory transistor 10C is formed on metal oxide layer 7 between the source wiring layer of the protective layer 31. the protective layer 31 with the metal oxide layer 7 at the channel region 7c. the protective layer 31 in the channel region 7c the contact of the first part called a channel protective layer 31c. metal oxide layer width of the channel direction 7 is larger than the gate electrode width of the channel direction 3. In this example, the protective layer 31 is set in a way of covering the metal oxide layer 7. the protective layer 31 is provided with the metal oxide layer 7 in the area of the two sides of the channel region 7c are exposed out of the opening 32 s, 32d. a source electrode 9 s and a drain electrode 9d are formed on the protective layer 31 and within opening 32 s, 32d, the opening 32 s, 32d in contact with the metal oxide layer 7. Thus, the metal oxide layer 7 in contact with source electrode 9 s area becomes the source contact region, and the drain electrode 9d contact area becomes the drain contact region.
In the memory transistor 10C, the same manner with the first embodiment, the drain electrode 9d overlapped with the metal oxide layer 7 and the gate electrode 3 when the two are viewed from the normal direction of the substrate 1 is formed by the first drain electrode metal layer 9d1, and does not include the second drain metal layer 9d2. For example, as shown, the opening 32d is only configured with a first drain metal layer 9d1, there is no configuration in the second drain electrode metal layer 9d2. This can obtain the same effect with the first embodiment. the source electrode 9 s of the structure is not particularly limited, for example, it may be arranged in the opening 32 s the first source metal layer 9s1 and the second source metal layer 9s2 both are overlapped with the metal oxide layer 7 and the gate electrode 3 both when viewed from the normal direction of the substrate 1. In addition, in FIG. 22, the channel region 7c of a planar shape of a rectangle, but may also be a U-shaped shown in FIG. 1 (b).
Next, referring to the drawings in an active matrix substrate manufacturing method as an example of the semiconductor device of this exemplary embodiment will be described.
FIG. 23 to FIG. 28 is for explaining manufacturing method of the active matrix substrate 1003 of an example of a process graph, each graph of (a) and (b) is a sectional view, (c) is a plan view. here represents for forming the memory transistor 10C on the active matrix substrate 1003, a capacitor portion 20, gate electrode contact 30 and the gate source cross part 40 of the procedure.
First, as shown in FIG. 23 (a) to (c), conductive film for forming a gate on the substrate 1, by the patterning to form a gate connecting portion 3sg, gate line G, the gate electrode 3C and the gate wiring layer of the capacitor line CS. then, forming a gate insulating film 5 in a manner covering the gate wiring layer. Next, the gate insulating film 5 formed on the oxide semiconductor film, by patterning and forming region R (10C) forming metal oxide layer 7C the memory transistor. In addition, the capacitor part forming region R (20) via a gate insulating film 5 overlapping with the capacitor line CS of the semiconductor layer 7cs is formed. a capacitor part forming region R (20) left on the semiconductor layer 7cs to a point different from the embodiment. material, thickness and forming method of each layer material and thickness of each layer, the forming method described in the first embodiment are the same.
Next, as shown in FIG. 24 (a) to (c), the gate insulating film 5, a metal oxide layer 7C and the semiconductor layer 7cs is formed on the insulating protective film, the patterned protective layer 31. the protection layer 31 at least on the metal oxide layer 7C becomes the channel area on the area. the position of the protective layer 31 in the channel region of a part is called a channel protective layer 31c.
when the insulating protective film is patterned in the gate insulation film below the insulating protective film 5 is also patterned. At this time, the metal oxide layer 7C and the semiconductor layer 7cs functions as an etch barrier layer, the gate insulating film 5 in the part will not covered by these layers is removed. In addition, by performing patterning of the gate source contact part forming region R (30), the protection layer 31 and the gate insulating film 5 to form the gate connecting part 3sg exposed by opening 33. the capacitor part forming region R (20), the protective layer 31 the opening for exposing the semiconductor layer 7cs 34 is formed. In addition, in the memory transistor formation region R (10C), the metal oxide layer 7C formed in a part of the two sides of the channel region 7cC are respectively formed so that the metal oxide layer 7C exposed by opening 32 s, 32d.
an insulating protection film, for example, can be formed using a plasma CVD method or a sputtering method, and by patterning using known dry etching. the insulating protective film is formed, for example, in the atmosphere of 450 ℃ to 200 temperature for annealing for 30 minutes to 4 hours. as an insulating protective film, for example, can be selected from the silicon oxide film (SiO2) and a silicon nitride film (SiN), a silicon oxynitride film (SiON), silicon oxynitride film (SiON), alumina (Al2O3) and single-layer tantalum oxide (Ta2O5) or more than 2 layers of laminated film. In this embodiment, as an example of SiO2 film is about 10nm to 500nm of the thickness.
Next, as shown in FIG. 25 (a) to (c), on the protective layer 31 and the protective layer 31 of the opening in the conductive film for forming a source electrode, after the patterning for the first time. with a conductive film to form a laminated film as the first metal film 9 L is the lower layer, the second metal film 9U as the upper layer as source electrode.
the first metal film 9 L and second metal film 9U is made with the same material as referring to FIG. 10. Here, for example, by sputtering continuously as the first metal film 9 L to form a Ti film (thickness: 10 to 100nm), forming an Al film as the second metal film 9U (thickness: 50 to 400nm). Thus, to obtain the source Ti film of double-layer structure film with a conductive film.
For the conductive film for the source electrode, for example using wet etching for patterning for the first time. wet etching only the second metal film 9U is etched without etching the first metal film 9 L is carried out. Thus, the second metal film 9U on the memory transistor 10C of a part of the metal oxide layer 7C to form an opening. opening the set portion comprises a metal oxide layer 7C formed in a whole area of the drain contact region and a partial region of the channel region. the first metal film 9 L exposed in the opening.
after the source forming a resist layer on the conductive film M, and then the source electrode conductive film for the patterning for the second time. the second patterning, such as resist layer as mask, using wet etching to remove the second metal film 9U, and then removed by dry etching the first metal film 9 L. Thus, to remove the first metal film 9 L and second metal film 9U, the metal oxide layer 7C in the region to be the channel region on the part (the source-drain separation).
Thus, as shown in FIG. 26 (a) to (c), in the memory transistor formation region R (10C) forming the source electrode 9sC and the drain electrode 9dC, the gate electrode contact part forming region R (30) forming the source electrode connecting part 9sg, the gate source cross part forming region R (40) forms a source wiring S, the capacitor forming region R (20) forms a capacitor electrode 9cs. the formed using source conductive film comprising these wiring and electrode layer referred to as a source wiring layer.
Here, the second metal film 9U is patterned by wet etching, therefore, the source electrode wiring layer, when viewed from the normal direction of the substrate 1. The end placed on the second metal film 9U than the end of the resist layer M is more closer to the inner side. and the first metal film 9 L by the dry etching for patterning, so when viewed from the normal direction of the substrate 1, the first metal film 9 L and the resist layer M end matching. in the profile so that, when viewed in a normal direction of the substrate 1 source wiring layer, and the second metal film 9U located on the first metal film 9 L. In the sectional view, the end of the second metal film 9U located on the first metal film 9 L. Furthermore, because the first patterning to form area of the drain contact region of the second metal film 9U is removed, so the drain contact region of the metal oxide layer 7C is only left on the first metal film 9 L. metal oxide layer 7C overlapped with the corresponding gate electrode 3C, and the source electrode region 9sC and the drain electrode 9dC becomes the channel region 7cC. In this embodiment, for example, the memory transistor forming region R (10A) such that the channel region 7cA when viewed from the normal direction of the substrate 1 is rectangular configured in the way the source electrode 9sC and the drain electrode 9dC.
so as to form the memory transistor 10C. For the storage transistor 10C same manner as with the first embodiment, the drain electrode 9d is overlapped with the metal oxide layer 7C and the gate electrode C both part composed of only the first metal film 9 L and does not include the second metal film 9U. On the other hand, the source electrode 9sC is overlapped with the metal oxide layer 7C and the gate electrode 3C both having a first metal film 9 L and second metal film 9U of the laminated structure.
and the gate source contact forming region R (30), obtaining the connection part 3sg contact with the gate in the opening part 33 of the source electrode connecting part 9sg. In addition, the gate source cross part forming region R (40) forms a source wiring S. the capacitor part forming region R (20) is formed in the opening 34 and the semiconductor contact layer 7cs the capacitor electrode 9cs. Therefore, the grid source electrode contact part forming region R (30) forms a gate source contact portion 30, the gate source cross part forming region R (40) form the gate source cross part 40, the capacitor part forming region R (20) forms a capacitor part 20, the memory transistor forming region R (10A, 10B) form a memory transistor 10A, 10B.
In addition, although not shown, pixel transistor 10T (refer to FIG. 5 (a), (b)) also can is formed with the memory transistor 10C by a common process. in the pixel transistor 10T, drain electrode of the second metal film 9U can be disposed on the metal oxide layer 7.
Next, as shown in FIG. 27 and FIG. 28 (a) to (c), forming a protective layer (passivation film) 11, a photosensitive resin such as an organic insulating film 13 and the upper conductive layer 17. firstly, using method similar to a method in the first embodiment, in order to form the protective film 11 and the organic insulating film 13. Next, the forming region R (30) is the gate source contact portion on the organic insulating film 13 is formed by part of the opening part. Then, the organic insulating film 13 as a mask for etching the passivation film 11. Therefore, to make the source electrode connecting part 9sg exposed to the surface of the contact hole 15. then, forming a conductive film on the organic insulating film 13 and in the contact hole 15, and patterned. Therefore, when the gate source contact portion formation region R (30) to obtain the connecting part 9sg in contact with the source electrode in the contact hole 15 on the conductive layer 17. protective film 11, organic insulating film 13, and the material and thickness of the conductive film, the material, thickness and forming method of the film forming method described in the first embodiment are the same. so as to obtain the active matrix substrate 1003.
memory transistor of this embodiment mode 10C has the etch barrier layer (etching baffle structure), and has no condition (channel etch structure) etch barrier layer has the following advantages.
In this embodiment, the channel region 7cC under the channel protective layer 31c covered state so as to separate the source electrode, drain electrode of source electrode by etching the conductive film. Therefore, compared with a thin film transistor having a channel etched structure, can reduce the etching damage to the channel region (7cC). deviation so as to improve electric characteristics of the memory transistor 10C. furthermore, it can reduce the electric characteristic variation caused by electrical stress. In addition, the gate electrode contact portion 30, the gate connecting portion 3sg and source connecting part 9sg directly. Thus, it can reduce the grid size of the source contact part 30, it is possible to reduce the circuit area.
(third embodiment)
the following illustrate the third embodiment of the semiconductor device of the invention. wherein, comprises memory transistor of bottom contact structure having an active layer on the source electrode and the drain electrode of the 10D points of the semiconductor device of this embodiment and the semiconductor device of the first embodiment. The other structures are the same.
FIG. 29 (a) and (b) shows an example of a plan view and a cross-sectional view 10D of the structure of the memory transistor in the third embodiment. FIG. 29 (b) shows section A-A ' shown in FIG. 29 (a) the section of the line. FIG. 29 to FIG. 1 marked with the same structural elements the same reference numerals and explanations are omitted.
in the storage transistor 10D on to cover the gate insulating film 5 of the gate electrode 3, the source electrode 9 s and the drain electrode 9d are separated, with the metal oxide layer 7 is formed therebetween. a metal oxide layer 7 is configured with the source electrode 9 s and the gate insulating film 9d between the drain electrode 5 and the source electrode 9 s and the drain electrode 9d on the surface and the side contact. when viewed from the normal direction of the substrate 1, a metal oxide layer 7 overlapped with the gate electrode 3 and between the source electrode 9 s and the drain electrode 9d part becomes the channel region 7c. In FIG. 29, a channel region 7c of a planar shape of a rectangle, but may also be a U-shaped shown in FIG. 1 (b).
in the embodiment, the drain electrode 9d is overlapped with the metal oxide layer 7 and the gate electrode 3 both when viewed from the normal direction of the substrate 1 is formed by the first drain metal layer 9d1, does not include the second drain metal layer 9d2. On the other hand, in the source electrode 9 s, is overlapped with the metal oxide layer 7 and the gate electrode 3 the two part comprises first and second source metal layers 9s1, 9s2. By adopting this configuration, it is possible to obtain the same effect with the first embodiment.
As shown, the first drain metal layer 9d1, the first source metal layer 9s1 and the second source metal layer 9s2 can be contacted with the lower surface of the metal oxide layer 7 (bottom contact structure). However, the second drain metal layer 9d2 preferably does not contact with the lower surface of the metal oxide layer 7.
Next, referring to the drawings in an active matrix substrate manufacturing method as an example of the semiconductor device of this exemplary embodiment will be described.
FIG. 30 to FIG. 34 is a process diagram of a manufacturing method of an example active matrix substrate, each image of (a) and (b) is a sectional view, (c) is a plan view. here represents a memory transistor formed on the active matrix substrate 10D and 10E, a capacitor 20, a gate source contact portion 30 and the gate source cross part 40 of the procedure. In addition, an active matrix substrate in this embodiment as long as it has the 2 memory transistors 10D and 10E, to any one can not have both.
Firstly, as shown in Figure 30 (a) to (c), conductive film for forming a gate on the substrate 1, by the patterning to form a gate connecting portion 3sg, gate lines G, gate electrodes 3D and 3E and the gate wiring layer of the capacitor line CS. then, forming a gate insulating film 5 in a manner covering the gate wiring layer.
Next, the gate insulating film 5 is formed on the laminated film to the first metal film 9 L as the lower layer, the second metal film 9U is the upper layer of the conductive film as the electrode, patterning for the first time.
the first metal film 9 L and second metal film 9U is made with the same material as referring to FIG. 10. Here, for example, by sputtering continuously as the first metal film 9 L to form a Ti film (thickness: 10 to 100nm), forming an Al film as the second metal film 9U (thickness: 50 to 400nm). Thus, to obtain the source Ti film of double-layer structure film with a conductive film.
For the conductive film for the source electrode, for example using wet etching for patterning for the first time. wet etching only the second metal film 9U is etched without etching the first metal film 9 L is carried out. Thus, the second metal film 9U located on the gate electrodes 3D, 3E the upper part forms an opening. the opening is configured to corresponding to the following part, the part comprises the step of after forming the metal oxide layer formed in a whole area of the drain contact region and a partial region of the channel region. the first metal film 9 L exposed in the opening.
Then, the conductive film for the source electrode is formed on the memory transistor 10D, 10E gate electrode 3D, 3E having an opening of a resist layer. Then, the source electrode conductive film for the patterning for the second time. the second patterning, such as resist layer as mask, using wet etching to remove the second metal film 9U, and then removed by dry etching the first metal film 9 L. Therefore, in the memory transistor formation region R (10D), R (10E), the source is formed with a conductive film are separated configuration of the source 9sA, 9sB and drain electrodes 9dA, 9dB (the source-drain separation). and the gate electrode contact part forming region R (30) forming the source electrode connecting part 9sg, the gate source cross part forming region R (40) forms a source wiring S, the capacitor part forming region R (20) forms a capacitor electrode 9cs. the formed using source conductive film comprising these wiring and electrode layer referred to as a source wiring layer.
Next, as shown in Figure 32 (a) to (c), forming an oxide semiconductor film on the gate insulating film 5 and the source electrode wiring layer, and patterning it. Therefore, in the memory transistor formation region R (10D) and R (10E) respectively forming a metal oxide layer 7D, 7E. the material and thickness of the oxide semiconductor film, forming method and material, thickness and forming method of the same embodiment.
metal oxide layers 7D, 7E are configured to respectively and located between the source electrodes 9sA and 7sB and the drain electrode 9dA, the gate insulation film 7dB between the contact 5 and the source electrodes 9sA, 7sB and drain electrodes 9dA, 7dB of the upper surface and the side contact. In this example, the metal oxide layer 7D in contact with the drain electrode 9dD of the first drain metal layer 9d1D, and is patterned metal layer 9d2D with the second drain contact. it can contact with the source electrode 9sD of the second source metal layer 9s2D. a metal oxide layer 7E is also the same. Therefore, when viewed from the normal direction of the substrate 1, the drain electrodes 9dD, 9dE are overlapped with the gate electrodes 3D, 3E and metal oxide layer 7D, 7E the two part does not comprise the second drain electrode metal layer 9d2D, 9d2E, it is possible to obtain the same effect with the embodiment. so as to form the memory transistor 10D, 10E.
In this embodiment, after the etching process of the conductive film for the source electrode to form a metal oxide layer 7D, 7E, so as to inhibit the etching process damage to the metal oxide layer 7D, 7E.
Next, as shown in Figure 33 and FIG. 34 (a) to (c), on the source wiring layer and the metal oxide layer 7D, 7E to form a protective film (passivation film) 11, a photosensitive resin such as an organic insulating film 13 and the upper conductive layer 17. First, by the same method embodiment, protective film 11 and organic insulating film 13 are formed in turn, and forming region R (30) is the gate source contact portion on the organic insulating film 13 is formed by part of the opening part. Next, the organic insulating film 13 as a mask for etching the passivation film 11. Therefore, it is possible to obtain the gate connecting portion 3sg and source connecting part 9sg exposed to the surface of the contact hole 15. then, forming a conductive film on the organic insulating film 13 and in the contact hole 15, and patterned. Thus, obtaining the source electrode connecting part 9sg electrically connected to the upper part of conductive layer 15 in the contact hole 17. protective film 11, organic insulating film 13, and the material and thickness of the conductive film, method for forming the material, thickness and forming method of the same embodiment. so as to obtain the active matrix substrate 1004.
memory transistor of this embodiment mode 10D, 10E has to contact with the source electrode and the drain electrode on the lower surface of the active layer 7A, 7B is formed in the way that the bottom contact structure. By adopting this structure, compared with the channel etch structure has the following advantages.
In this embodiment, the operation for the source, drain and source electrode by etching process of the conductive film after forming a metal oxide layer 7D, 7E. Therefore, compared with a thin film transistor having a channel etched structure can reduce the etching damage of the channel region 7cD, 7cE. so as to improve electric characteristics of the memory transistor 10D, 10E bias. furthermore, it can reduce the electric characteristic variation caused by electrical stress.
Furthermore, in the present embodiment, and the second embodiment has etching baffle structure as compared with a case of manufacturing process is simplified. Therefore, it can reduce the manufacture cost and improve the yield.
action, action and electric characteristic of the memory transistor of the second embodiment and third embodiment 10C to 10E explained in the first embodiment and the same electric characteristics. Moreover, these embodiments are also same manner with the first embodiment, is not limited to an active matrix substrate, and it can be widely applied to an electronic device including an integrated circuit comprising: a memory circuit and so on.
In addition, in the respective embodiments, as the memory transistors 10A to 10E using a bottom-gate type thin film transistor, but also can use a top-gate type thin film transistor.
FIG. 36 (b) and (c) is an example illustrating the top gate type memory transistor of the structure section picture. in the example shown in FIG. 36 (b), except gate electrode 3 configured outside the metal oxide layer 7 above this point with the memory transistor shown in FIG. 34 10D and 10E are the same structure. FIG. 36 (c), in addition to changing the first metal film 9 L and second metal film 9U laminated in this point, with FIG. 36 (a) shows the memory transistor have the same structure.
In the semiconductor device of this exemplary embodiment, the memory transistor 10A of the write operation using the metal oxide layer 7A to generate Joule heat. when a write operation in the tunnel region 7cA of temperature such as above 200 ℃. a drain-side of the channel region 7cA, it is possible to be more (e.g., more than 250 ℃ or more than 300 ℃). Therefore, the memory transistor 10A of the above metal oxide layer 7A, preferably is not configured with low heat resistance material (softening temperature: less than 200 ℃, preferably less than 300 ℃) layer (such as an organic insulating film). the following example will be described more specifically using active matrix substrate.
the active matrix substrate 1002 to 1004, memory transistors 10A to 10E covered by the passivation film 11 and the organic insulating film 13. If the low resistance of the organic insulating film 13, according to the different write conditions, etc., the organic insulating film 13 on the metal oxide layer portion may be stripped from the passivation film 11, or changed. In particular, the end of the organic insulating film 13, a metal oxide layer on a drain side, peeling or deformation may occur. memory transistor RT if there is peeling or deformation of the organic insulating film 13, for example, using a plurality of memory transistor memory array. The peeling and deformation of the organic insulating film 13 is capable of identifying the possible positions is written with the memory transistor ST is not written.
an inorganic insulating film (silicon oxide film above-listed) Therefore, as shown in FIG. 35 (a) to (c) shows an example of the above, the above metal oxide layer 7A, as a passivation film 11, can be provided with heat resistance is high, and no organic insulating film 13 is formed on the passivation film 11. Therefore, it will not occur the problem caused by writing of the heat, which can further improve the reliability and safety of the device.
FIG. 35 (a) to (c) as an active matrix substrate for example may not have organic insulating film as the planarization film. or, it may only has organic insulating film 13 on the substrate 1 the one part area. In this case, the organic insulating film 13 is not formed on the memory transistor 10A, 10C, 10D of the metal oxide layer 7A, 7C and 7D above, for example, the pixel transistor for the circuit using the above metal oxide layer of the transistor may be formed with an organic insulating film 13.
In FIG. 5 the example of the active matrix substrate 1002, the organic insulating film 13 can be formed on the plurality of pixel transistors 10T above, but 10A is not formed above the memory transistor in the memory circuit. For example, the organic insulating film 13 can be set in the display area 100, but not provided on the peripheral region 200 (storage circuit is at least in peripheral region 200).
Alternatively, the active matrix substrate 1002 to 1004 instead of the organic insulating film 13 using a material of high heat resistance (e.g., softening temperature: more than 200 ℃, preferably more than 300 ℃) of the planarization film, also can suppress the problem caused by writing of the heat. For example, as the planarization film can use inorganic SOG (spin on glass) film as the inorganic insulating film.
In addition, in the various embodiments, storage transistors 10A and 10B are thin-film transistors, but may also be a MOS type transistor. even if the MOS type transistor, flows in the channel region by the drain current of the high current density, it is possible to make it change as resistor state. MOS-type transistor has a separated structure of the insulating film is metal oxide semiconductor film on a silicon substrate, for example. in this structure, while using the silicon substrate high thermal dissipation, but because the silicon substrate with the oxide semiconductor film separated by an insulating film, so it can restrain the Joule heat caused by the write current emitted to the silicon substrate. Therefore, it is possible to use Joule heat to make low resistance of the oxide semiconductor film.
each conduction film forming the memory transistors 10A to 10E and material, structure, thickness and transistor characteristics and write characteristics of each insulating film and is not limited in the embodiment example illustrated content.
In addition, with the n-channel memory transistor 10A to semiconductor device 10E as an example for the explanation of the embodiment, but the conductive type memory transistors are not limited to the n-channel type or may be a p-channel type. under the condition of the p-channel memory transistor, the drain current Ids to flow from source to drain. the p-channel memory transistor, by applying the embodiments of the electrode structure, it is possible to inhibit the writing caused by the thermal injury.
Industrial availability
The invention can be widely applied to a memory circuit having a semiconductor device and an electronic device. for example, can be applied to a nonvolatile semiconductor memory device, an integrated circuit (IC, LSI) active matrix substrate in the liquid crystal display device or an organic EL display device and other display device, each display device used.
Figure explanation
1 substrate
3 gate electrode
3sg grid connection part
5 gate insulating film
7 metal oxide layer
7c channel region
9d drain electrode
9d1, 9d2 drain electrode metal layer
9 s source electrode
9s1, 9s2 source electrode metal layer
9 L first metal film
9U second metal film
9cs capacitor electrode
9sg source electrode connecting part
10A to 10E memory transistor
10T the pixel transistor
11 protective film (passivation film)
13 organic insulating film
15 contact hole
17 upper part conduction layers
18 an upper gate electrode
19 pixel electrode
20 capacitor part
30 source contact part
31 protective layer
40 source cross part
100 display area
101 pixel
200 periphery area
201 terminal part
1001 semiconductor device
1002, 1003 and 1004 active matrix substrate
CS capacitor wiring
G gate wiring
S source electrode wiring
Claims
A semiconductor device, wherein it comprises substrate and is support on the substrate of at least one of the storage transistor, wherein the semiconductor device is wherein: at least one of the storage transistor is from drain electrode current can Ids depending on gate voltage Vg semiconductor state and non-reversible change of drain current to Ids not dependent on resistor body state gate voltage Vg of the storage transistor, at least one of the storing transistor comprises gate electrode, metal oxide layer, the second metal arrangement of gate insulation film on the gate electrode and the metal oxide layer and between the metal oxide layer and electric connected with the electrode and drain electrode source electrode, the drain electrode comprises the first leakage pole comprises metal layer and the second leakage pole metal layer of laminated structure, the first leakage pole metal layer of melting point is 1200 ℃ more than the metal forming the first, the second leakage pole metal layer of melting point lower than the first metal and forming, when in the normal direction from the surface of said substrate observation. One part the metal oxide layer and the gate electrode and the drain electrode of the two and two overlapping, said drain electrode and said one portion containing the first leakage pole metal layer and not including the second leakage pole metal layer.
The semiconductor device according to claim 1, wherein the source pole set with comprises the first source electrode metal layer and the second pole source pole metal layer of laminated structure, the first source pole metal layer comprising the first metal, the second source pole metal layer comprising the second metal, when in the normal direction from the surface of said substrate observation, one part and the metal oxide layer and the gate electrode the source electrode of the double pole and this overlap, the source pole of the one electrode portion includes said first source pole metal layer and said the second source pole metal layer.
The semiconductor device according to claim 1, wherein the source pole set with comprises the first source electrode metal layer and the second pole source pole metal layer of laminated structure, the first source pole metal layer comprising the first metal, the second source pole metal layer comprising the second metal, when in the normal direction from the surface of said substrate observation, one part and the metal oxide layer and the gate electrode the source electrode of the double pole and this overlap, the source pole of the one electrode portion includes said first source pole metal layer and not containing the second source pole metal layer.
The semiconductor device according to any one of claims 1 to 3, wherein the upper surface of said the first leakage pole metal layer and the metal oxide layer directly contact.
The semiconductor device according to any one of claims 1 to 3, wherein the lower surface of the first leakage pole metal layer and the metal oxide layer directly contact.
The semiconductor device according to any one of claims 1 to 5, wherein the grid electrode is the metal oxide layer of the substrate one side.
The semiconductor device according to any one of claims 1 to 6, wherein said first leakage pole metal layer and said second leakage pole metal layer from the side of the substrate in sequence.
The semiconductor device according to any one of claims 1 to 7, wherein the substrate normal direction of observation, and separate in the metal oxide layer with the gate insulation film and the gate electrode overlap and the said source pole electrode and the portion between the drain electrode has a U shape.
The semiconductor device according to any one of claims 1 to 8, wherein the first metal is selected from the metal of W, Ta, Ti, Mo and Cr or the alloy.
The semiconductor device according to any one of claims 1 to 9, wherein the melting point of the second metal less than 1200 ℃.
The semiconductor device according to any one of claims 1 to 9, wherein the second metal is selected from the metal of Al and Cu.
The semiconductor device according to any one of claims 1 to 11, wherein said metal oxide layer comprising In, Ga and Zn.
The semiconductor device according to claim 12, wherein the metal oxide layer comprises crystalline portion.
The semiconductor device according to any one of claims 1 to 13, wherein at least one of the storage transistor as storage transistor ST and the body state includes the state of the storing transistor semiconductor of RT.
The semiconductor device according to any one of claims 1 to 11, wherein it also comprises support equipped on the substrate of the semiconductor with layer containing metal oxide and the other is transistor, the other transistor of the said semiconductor layer and the storage transistor is metal oxide layer of the oxide semiconductor film forming a common, the other transistor of the source electrode and drain electrode comprises electrode comprises the first metal layer and the second metal layer is laminated structure, the first metal layer comprising the first metal, the second metal layer comprising the second metal, one part drain electrode when in the normal direction from the surface of said substrate observation, the other and of the transistor and the other transistor of the gate electrode and the metal oxide layer the two and two overlapping, the other transistor and the drain electrode of said one part including the first metal layer and the second metal layer.
The semiconductor device according to any one of claims 1 to 15, wherein said semiconductor device is active region matrix substrate, comprises: a display area, the display area comprises multiple pixel electrode and one pixel transistor; and the periphery are respectively and in the multiple of pixel electrode corresponding to the pixel electrode is connected with the power, the peripheral region and are arranged in the display region and comprises more than one circuit, the multi-circuit comprises one set with at least one of the storage transistor and storage circuit, said pixel transistor and of the whole multi-transistor in the periphery region and forming the multi-circuit and of the at least one individual, and with at least one of the storage transistor is the metal oxide layer using common oxide semiconductor film but forming the semiconductor layer.
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