Prosecution Insights
Last updated: August 17, 2026
Application No. 18/767,871

Display Device

Non-Final OA §102§103
Filed
Jul 09, 2024
Priority
Oct 30, 2023 — RE 10-2023-0146456
Examiner
TSO, STANLEY
Art Unit
Tech Center
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
384 granted / 506 resolved
+15.9% vs TC avg
Strong +33% interview lift
Without
With
+33.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
40 currently pending
Career history
534
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
53.3%
+13.3% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
16.3%
-23.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 506 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Ha” (US 2022/0181563). Regarding claim 1, Ha anticipates 1. A display device comprising: a display panel including an active area and a non-active area (Figs. 1A, 1B, [0033]-[0037]; the display panel 10 includes the display area DA and the non-display area NDA); and a driving chip in the non-active area (Figs. 1A, 1B, [0033]-[0037]; the driving chip 120 is in the non-display area), wherein the display panel includes a crack prevention pattern (Figs. 1A, 1B, [0033]-[0037]; the display panel 10 includes the crack prevention layer 130), and at least a portion of the crack prevention pattern overlaps an edge of one short side of the driving chip (Figs. 1A, 1B, [0033]-[0037]; the crack prevention layer 130 overlaps an edge of one short side of the driving chip 120). Regarding claim 2, Ha anticipates 2. The display device of claim 1, wherein the crack prevention pattern is in the non-active area in a direction parallel to the edge of one short side of the driving chip (Figs. 1A, 1B, [0033]-[0037]; the crack prevention layer 130 is in the non-display area in a direction parallel to the edge of one short side of the driving chip 120). Regarding claim 3, Ha anticipates 3. The display device of claim 1, wherein the crack prevention pattern is electrically floating (Fig. 5, [0066], the crack prevention layer 130 overlaps the insulation layer 116 is not grounded and is electrically floating). Regarding claim 4, Ha anticipates 4. The display device of claim 1, wherein the crack prevention pattern is on both short sides of the driving chip parallel to the short side of the driving chip such that at least a portion of the crack prevention pattern overlaps edges of both short sides of the driving chip (Figs. 1A, 1B, [0033]-[0037]; the crack prevention layer 130 is on both short sides of the driving chip parallel to the short side of the driving chip 120 such that at least a portion of the crack prevention layer 130 overlaps edges of both short sides of the driving chip 120). Regarding claim 5, Ha anticipates 5. The display device of claim 1, wherein at least a portion of the crack prevention pattern overlaps the edge of the driving chip (Figs. 1A, 1B, [0033]-[0037]; at least a portion of the crack prevention layer 130 overlaps the edge of the driving chip 120). Regarding claim 6, Ha anticipates 6. The display device of claim 5, wherein the crack prevention pattern overlaps four points of the edge of the driving chip (Figs. 1A, 1B, [0033]-[0037]; the crack prevention layer 130 overlaps four points of the edge of the driving chip 120). Regarding claim 10, Ha anticipates 10. The display device of claim 1, wherein the crack prevention pattern is spaced apart from a bump of the driving chip (Fig. 5, [0033]-[0037], [0060]-[0064]; the crack prevention layer 130 is spaced apart from the bumps 115a and 115b of the driving chip 120). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 7-8 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ha in view of “Hwang” (US 2018/0204901). Regarding claim 7, Ha discloses the claimed invention as applied to claim 1, above. Ha discloses 7. The display device of claim 1, wherein the display panel comprises: a substrate (Fig. 5, [0033]-[0037], [0060]-[0064]; the circuit driving element 100 is a substrate); an insulating layer stacked in the non-active area on the substrate (Fig. 5, [0033]-[0037], [0060]-[0064]; the film 110 is an insulating layer); a planarization layer on the crack prevention pattern on the insulating layer (Fig. 5, [0033]-[0037], [0060]-[0064]; the insulation layer 116 is a planarization layer on the crack prevention layer 130 on the film 110); and a first pad that is spaced apart from the crack prevention pattern (Fig. 5, [0033]-[0037], [0060]-[0064]; the first pad 112 is spaced apart from the crack prevention layer 130), wherein the planarization layer is on the insulating layer exposed to a space between the crack prevention pattern and the first pad (Fig. 5, [0033]-[0037], [0060]-[0064]; the insulation layer 116 is on the film 110 exposed to a space between the crack prevention layer 130 and the first pad 112), and the planarization layer is on a side of the first pad (Fig. 5, [0033]-[0037], [0060]-[0064]; the insulation layer 116 is on a side of the first pad 112). Ha does not disclose a plurality of insulating layers stacked on the substrate. Hwang discloses a plurality of insulating layers stacked on the substrate (Fig. 10, [0113], [0114], [0116]; the stack of insulating layers 160a, 160b, and 160c includes the crack prevention pattern 180). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device with Hwang’s crack prevention patterns in order to mitigate the progress of cracks in the substrate of a display device, as suggested by Hwang at [0007]. Regarding claim 8, Ha in view of Hwang discloses the claimed invention as applied to claim 7, above. Ha discloses 8. The display device of claim 7, wherein the edge of one short side of the driving chip overlaps the planarization layer and the crack prevention pattern (Fig. 5, [0033]-[0037], [0060]-[0064]; the edge of one short side of the driving chip 120 overlaps the insulation layer 116 and the crack prevention layer 130). Regarding claim 11, Ha discloses the claimed invention as applied to claim 1, above. Ha does not disclose the limitations of claim 11. Hwang discloses 11. The display device of claim 1, wherein the crack prevention pattern is in an embossed pattern including a metal layer (Fig. 10, [0108], [0113], [0114], [0116]; the crack prevention pattern 180 is an embossed pattern and includes a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device with Hwang’s crack prevention patterns in order to mitigate the progress of cracks in the substrate of a display device, as suggested by Hwang at [0007]. Regarding claim 12, Ha discloses the claimed invention as applied to claim 1, above. Ha does not disclose the limitations of claim 12. Hwang discloses 12. The display device of claim 1, wherein the crack prevention pattern includes a same material as that of source/drain electrodes or a gate electrode of a switching transistor in the active area (Fig. 10, [0108], [0113], [0114], [0116]; the crack prevention pattern 180 includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device with Hwang’s crack prevention patterns in order to mitigate the progress of cracks in the substrate of a display device, as suggested by Hwang at [0007]. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ha in view of Hwang and Murakami (US 2024/0251618). Regarding claim 9, Ha in view of Hwang discloses the claimed invention as applied to claim 7, above. Ha does not disclose the limitations of claim 9. Murakami discloses 9. The display device of claim 7, further comprising: an anisotropic conductive film between the driving chip and the first pad, wherein the anisotropic conductive film overlaps at least a portion of the planarization layer and the crack prevention pattern at the edge of one short side of the driving chip (Fig. 11, [0063], [0117]; the anisotropic conductive film 65 is between the chip 60 and the terminal 18g and overlaps the edge of the chip 60). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device, as modified by Hwang, with Murakami’s anisotropic conductive film in order to restrain the warping of the panel at the first output terminals, which in turn enables restraining breakage, as suggested by Murakami at [0117]. Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ha in view of “Lee” (US 2023/0016849). Regarding claim 13, Ha discloses the claimed invention as applied to claim 1, above. Ha discloses a first pad which is disposed in the non-active area; and a second pad which is disposed in an opposite direction while facing the first pad, wherein the first pad and the second pad overlap both long sides of the driving chip (Fig. 5, [0033]-[0037]; the first and second pads 112, 114 are disposed in an opposite direction to each other and overlap long sides of the driving chip 120). Ha does not disclose a first pad which is disposed toward the active area; and a second pad which is disposed in an opposite direction to the active area while facing the first pad, and wherein the crack prevention pattern is spaced apart from the first pad and the second pad so as not to overlap the first pad and the second pad. Lee discloses a first pad which is disposed toward the active area; and a second pad which is disposed in an opposite direction to the active area while facing the first pad, and wherein the crack prevention pattern is spaced apart from the first pad and the second pad so as not to overlap the first pad and the second pad. (Figs. 1B, 2, [0031]-[0032], [0035], [0037]; the semiconductor die 106 is a flip-chip which includes middle conductive pads 1061 on each side of the die 106, the crack prevention design includes connected line segments 301 and 302, the line segments 301 and 302 and their intersection S1 are located in each stress concentration area die corner area C which is spaced apart from the first and second pads 1061). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device with Lee’s crack prevention patterns spaced apart from each other in order to mitigate effects of the stress concentration areas SA in the package substrate 104 are close to the die corner areas C of the semiconductor die 106, as suggested by Lee at [0035]. Regarding claim 15, Ha discloses the claimed invention as applied to claim 1, above. Ha does not disclose the limitations of claim 15. Lee discloses 15. The display device of claim 1, wherein at least a portion of the crack prevention pattern does not overlap edges of both short sides of the driving chip, and the display panel comprises a plurality of crack prevention patterns spaced apart from each other to overlap four points of the edge of the driving chip (Fig. 2, [0035], [0037]; the conductive line with crack prevention design includes connected line segments 301 and 302, the line segments 301 and 302 and their intersection S1 are located in each stress concentration area, die corner area SA under the shadow of the semiconductor die 106). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device with Lee’s crack prevention patterns spaced apart from each other in order to mitigate effects of the stress concentration areas SA in the package substrate 104 are close to the die corner areas C of the semiconductor die 106, as suggested by Lee at [0035]. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ha in view of Lee and Hwang. Regarding claim 14, Ha in view of Lee discloses the claimed invention as applied to claim 13, above. Ha does not disclose the limitations of claim 14. Hwang discloses 14. The display device of claim 13, wherein the crack prevention pattern includes a same material as that of the first pad or the second pad (Fig. 10, [0108], [0113], [0114], [0116]; the crack prevention pattern 180 includes a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like). It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ha’s display device, as modified by Lee, with Hwang’s crack prevention patterns in order to mitigate the progress of cracks in the substrate of a display device, as suggested by Hwang at [0007]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANLEY TSO/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Jul 09, 2024
Application Filed
Jul 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+33.2%)
2y 3m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 506 resolved cases by this examiner. Grant probability derived from career allowance rate.

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