DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for the examination.
§ 101 2. 35 U.S.C. 101 reads as follows
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
2.Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
3. As to Claims 1, 8, 15 have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ indicate a stream; a dependencies parameter to indicate an array of nodes; a numDependencies parameter to indicate a size of the array in dependencies; and a flags parameter to indicate how to update a dependency set. ” recite a mental process since “ indicate ” is function that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ wherein the one or more core complexes include one or more central processing unit (CPU) cores; one or more graphics complexes, wherein the one or more graphics complexes include one or more compute units (CUs); an L2 cache; one or more fabric interconnects; a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface; wherein: the processor is to perform a stream update capture dependencies (StreamUpdateCaptureDependencies) application program interface (API) to update a set of dependencies in a capturing stream ” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ wherein the one or more core complexes include one or more central processing unit (CPU) cores; one or more graphics complexes, wherein the one or more graphics complexes include one or more compute units (CUs); an L2 cache; one or more fabric interconnects; a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface; wherein: the processor is to perform a stream update capture dependencies (StreamUpdateCaptureDependencies) application program interface (API) to update a set of dependencies in a capturing stream;” this generally have been a mental process although the central processing unit (CPU) cores; one or more graphics complexes, wherein the one or more graphics complexes include one or more compute units (CUs); an L2 cache; one or more fabric interconnects; a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface could be a generic computer component if the spec describes it as actual computer hardware, amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
4. As to Claims 5, 6, 19, 20, have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ indicate whether the dependency set is to be added to an existing set, indicate whether the dependency set is to replace an existing set ” recite a mental process since “ indicate ” is function that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ wherein the one or more core complexes include one or more central processing unit (CPU) cores; one or more graphics complexes, wherein the one or more graphics complexes include one or more compute units (CUs); an L2 cache; one or more fabric interconnects; a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface; wherein: the processor is to perform a stream update capture dependencies (StreamUpdateCaptureDependencies) application program interface (API) to update a set of dependencies in a capturing stream ” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ wherein the one or more core complexes include one or more central processing unit (CPU) cores; one or more graphics complexes, wherein the one or more graphics complexes include one or more compute units (CUs); an L2 cache; one or more fabric interconnects; a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface; wherein: the processor is to perform a stream update capture dependencies (StreamUpdateCaptureDependencies) application program interface (API) to update a set of dependencies in a capturing stream;” this generally have been a mental process although the central processing unit (CPU) cores; one or more graphics complexes, wherein the one or more graphics complexes include one or more compute units (CUs); an L2 cache; one or more fabric interconnects; a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface could be a generic computer component if the spec describes it as actual computer hardware, amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
5. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible.
Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
7. A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
8. The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
6. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
7. Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Application number: 17720247, and claims 1-20 of U.S Application number : 18767878 . Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-24 of US applications 17720247, claims 1-20 of US applications 18767878 contain(s) , Claims 1-20 of US Application 18767873 every element of claim(s) 1-20 of the instant application and thus anticipate the claim(s) of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim(s) 1, 8, 15 are rejected under 35 U.S.C. 103 as being unpatentable over SANKARAN( US 20200401440 A1) in view of Kogelman( US 11573772 B2) in view of in view of Manion( US 20040111469 A1 ) and further in view of Slesarenko( US 20160139894 A1).
As to claim 1, Sankaran teaches acceleration processor unit (APU) comprise more core complexes, wherein the one or more core complexes include one or more central processing unit (CPU) cores; one or more graphics complexes( using pre-defined APIs that read and update the graph data (as illustrated in the bottom portion of program code), para[0954], ln 10-15/ FIG. 126B shows processor core 12690 including a front end unit 12630 coupled to an execution engine unit 12650, and both are coupled to a memory unit 12670. The core 12690 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 12690 may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like, para[0030], ln 1-12),
wherein the one or more graphics complexes include one or more compute units (CUs)( deploy accelerator solutions and manage the complexity of portably utilizing accelerators as there is a wide spectrum of stock units and platforms which implement different mixes of accelerators. , para[0151], ln 1-5/ Examples of accelerators include, but are not limited graphics processing units (“GPUs”), fixed-function field-programmable gate array (“FPGA”) accelerators, and fixed-function application specific integrated circuits (“ASICs”). Note that an accelerator, in some implementations, may be general purpose central processing unit (“CPU”) if that CPU is more efficient than other processors in the system., para[0151], ln 20-29)/ a CPU with the special purpose logic 12808 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 12802A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 12802A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 12802A-N being a large number of general purpose in-order cores. Thus, the processor 12800 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor, para[1143]);
an L2 cache, one or more fabric interconnects( its own cache (e.g., L1 and L2), para[0209], ln 5-9/ Further, dies and other components can themselves include interconnect or other communication fabrics (e.g., 12035, 12050) providing the infrastructure for communication between components (e.g., 12025-12030 and 12040-12045), para[0346], ln 10-17)
a memory controller; and one or more input/output (I/O) interfaces comprising a peripheral component interconnect express (PCIe) interface( FIG. 128 is a block diagram of a processor 12800 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention, para[1142], ln 1-5)/ such that the third protocol comprises the Peripheral Component Interface Express (PCIe) protocol, para[1472]/ A plurality of input/output interfaces (e.g., PCIe, common link detailed below) 11911 connect the processor 11901 to external devices such as other processors and accelerators, para[0216]);
Kogelman teaches perform a stream update capture dependencies(the processors(s) 604 may include a central processing unit (CPU), a graphics processing unit (GPU), both CPU and GPU, a microprocessor, a digital signal processor or other processing units or components known in the art. , col 9, ln 60-67/ These operations may be performed with respect to the visual graph-based code or an intermediate representation of the visual graph-based code generated for input to an API of the build module 104[API], col 4, ln 12-18/ Such visual graph-based code may include visual graph-based programming language instructions using a node and edge syntax that may form a directed graph of operations. The nodes may represent functions or operations. For example, one or more of the nodes may be native function call nodes of the visual graph-based programming language (e.g., assignment, add, square, square root, etc.). The edges between nodes may represent data flows (e.g., input and output of variables or values) and/or control between nodes flows (e.g., to provide a direction to the directed graph), col 2, ln 5-17/ the build module 104[api] may generate combined code including a third plurality of nodes by injecting the subgraph into the first plurality of nodes in place of the text-based node. For examples, input edges to the text-based node may be redirected to serve as inputs to a node of the subgraph (e.g., the first node or function node) and input edges to the text-based node may be redirected to serve as output from a node of the subgraph (e.g., a last node or exit node of the subgraph). As with the injectable code 114, the combined code may be in the visual graph-based programming language or may be in an intermediate representation (e.g., node and pin), col 5, ln 64-67 to col 6, ln 1-9),
the APU is to perform a stream update capture dependencies (StreamUpdateCaptureDependencies) application program interface (API) to update a set of dependencies in a capturing stream(the processors(s) 604 may include a central processing unit (CPU), a graphics processing unit (GPU), both CPU and GPU, a microprocessor, a digital signal processor or other processing units or components known in the art. , col 9, ln 60-67/ The build module 104 may interpret the text-based code 112 of the text-based node 110 into an injectable code 114 which may be equivalent in function to the text-based code 112 (e.g., a graph-based code equivalent to in function to the text-based code 112 but in the syntax of the visual graph-based code or an intermediate representation of the visual graph-based code generated for input to an API of the build module 104). For example, the build module 104 may parse the text-based code 112 to determine operations invoked by the text-based statement of the text-based code 112. The build module 104 may generate nodes in the graph-based code that perform the determined operations. In some examples, the determination of nodes that perform the operation may be based on the operation and the variable types of input and outputs of text operations and the possible graph-based nodes that may be selected. The build module 104 may then connect or pin the inputs and outputs of the generated nodes to form a subgraph (e.g., the injectable code 114) , col 4, ln 5-51/ Once the subgraph of graph-based nodes has been generated, the build module 104 may inject the injectable code 114 into the original graph-based code at the location of the text-based node 110 to form combined code comprising combined nodes and edges including the nodes and edges of the original graph-based code with the nodes and edges of the injectable code 114 substituted in place of the text based node 110, col 4, ln 52-60).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this generates a combined code based on the first plurality of nodes and the second plurality of nodes and compile the combined code.
Manion teaches wherein the StreamUpdate Dependencies API is to use: a stream parameter to indicate a stream( Once a record has been created or retrieved, an application can either update or delete the record. If an application wishes to update a record, it simply updates the fields it wishes and calls a peer graph update record API. This API updates the record in the database and floods the record to each node in the graph. Finally, a record can be deleted from the graph by calling a peer graph delete record API. It is important to note that this API does not actually remove the record from the database. Rather, it marks the record for deletion and floods this deletion to the rest of the graph. The record is not removed from the database until it expires, para[0078]/ the peer graph add record API is used to add a new record to the graph as introduced above. A record added with this API is flooded to each node in the graph. The parameters for this API include the graph handle, a pointer to record data, and a pointer that is set to the record ID that uniquely identifies a record in a graph, para[0082], ln 3-10/The peer graph update record API introduced above updates a record within the graph. Further, this function updates the version number, and floods the record to each node in the graph. The parameters for this function include the graph handle, and a pointer to the new data to associate with record. The fields in the record that can be modified are the size, the flags, the attributes, the expiration time (to a higher expiration time), the security data, and the data itself, para[0083], ln 1-12);
and a flags parameter to indicate how to update a dependency set( The peer graph delete record API, as discussed above, marks a record as deleted within the graph. This API does not actually remove the record from the database. Rather, it marks the record as deleted and floods it to the graph. This is done to ensure that each node in the graph has an identical view of the database. The parameters for this API are the graph handle, a pointer to the record ID to delete, and a local flag. If this flag is set true, this API does not flood the deletion to other nodes in the graph. Rather, the API just removes it from the local database. This API returns an indication of success or failure, para[0084], ln 1-18).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides new and improved P2P application programming interfaces (APIs) and methods for the creation and access of graphs, the retrieval of node and graph information, the addition, modification, deletion and management of records (data).
Slesarenko teaches a dependencies parameter to indicate an array of nodes; a numDependencies parameter to indicate a size of the array in dependencies( First, it is graph-based, i.e. it is a “graph data structure” with some specific information stored inside graph nodes. Second, it can be implemented in an object-oriented language. Nodes of the graph-based IR correspond to operations of the source program. Edges correspond to dataflow between operations. The order of execution of operations is not explicitly specified by the graph and is dictated by dependencies between the nodes., para[0006], ln 10-19/The graph building process 600 is shown in FIG. 6. It is a step-by-step construction of the graph shown in FIG. 3. At line 1, a graph ‘g’ is constructed by the function ‘new Graph( )’. At line 2, the symbol ‘an’ is set to the function ‘g.addNode(new Var( )’. At line 3, the symbol ‘sum’ is set to the function ‘g.addNode(new FloatArraySum(arr))’. At line 4, the symbol ‘len’ is set to the function ‘g.addNode(new FloatArrayLength(arr))’. At line 5, the symbol ‘res’ is set to the function ‘g.addNode(new FloatDiv(sum, len))’. The edges of the graph are represented by symbols that are stored in nodes. For example ‘FloatDiv’ node keeps the symbols ‘sum’ and ‘len’ for two operands of the operation, para[0012]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this allows implementing graph-based intermediate representation in an object-oriented language to easily support generic programs.
As to claims 8, 15, they are rejected for the same reason as to claim 1 above.
9. Claim(s) 2, 3, 9-10, 16, 17 are rejected under 35 U.S.C. 103 as being unpatentable over SANKARAN( US 20200401440 A1) in view of Kogelman( US 11573772 B2) in view of Manion( US 20040111469 A1 ) in view of Slesarenko( US 20160139894 A1) and further in view of MOLA(US 20190220403 A1).
As to claim 2, Mola teaches the capturing stream is a stream in capture mode( This is captured with the solid arrow from node 909 to node 913, and the value (data D) can be added to decoupled data stream 1002. Again, this is newly logged data, and a resolved dependency. At ID14 (node 910) there is a dependency on P0 at address @1, much like IDS, which could again be ID1 (node 901), ID10 (node 904), or ID19 (node 905). As such, graph 900 shows dashed arrows from node 910 to each of nodes 901, 904, and 905. At ID15 (node 911) the read has a dependency on P2, which is the write at ID13 (node 914). This is captured with the solid arrow from node 911 to node 914, and the value (data F) can be added to decoupled data stream 1002, para[0135], ln 17-30).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this identifies the dependencies, determinizes any appropriate values, and records new trace data streams, and/or augmenting existing trace data stream(s), so that they can be replayed in a thread-independent manner.
As to claim 3, Mola the stream is the capturing stream; and the dependency set is the set of dependencies in the capturing stream( para[0135], ln 7-30) for the same reason as to claim 2 above.
As to claims 9-10, 16, 17, they are rejected for the same reason as to claims 2-3 above.
10. Claims 4, 11, 18 are rejected under 35 U.S.C. 103 as being unpatentable over
SANKARAN( US 20200401440 A1) in view of Kogelman( US 11573772 B2) in view of Manion( US 20040111469 A1 ) in view of Slesarenko( US 20160139894 A1) and further in view of Taylor( US 20160210724 A1).
As to claim 4, Taylor teaches the dependency set is the array of nodes( Source node 110 and destination node 150 are each a data array or data stream entered into the graph explicitly, para[0036], ln 15-20/ The graph edges 111, 112, 113, 114 are provided by the image processing software developer to define the flow of the data array/data stream from source node 110 through the compute nodes 120, 130, 140, to destination node 150. The graph-based implementation API provides function(s) for connecting an image graph, for example:Connect Graph, para[0044], ln 7-16).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides a graph-based image processing implementation API to provide implementers with the information needed to make task/work assignments and scheduling decisions that may, for example, improve efficiency through parallelism.
As to claims 11,18, they are rejected for the same reason as to claims 4 , 18 above.
11. Claims 5, 6, 12, 13, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over SANKARAN( US 20200401440 A1) in view of Manion( US 20040111469 A1 ) in view of Slesarenko( US 20160139894 A1) and further in view of Bates( US 5701489 A).
As to claim 5, Bates teaches wherein the flags parameter is to indicate whether the dependency set is to be added to an existing set( FIG. 5 is a flow chart diagram showing the details of procedure body reduction process 60 in FIG. 4. Procedure 60 begins by clearing the MoveToStatic global variable table at step 64. A CFG construction process 66 is then initiated to construct a control flow graph (CFG) representing the rejected procedure body. After CFG construction, a CFG annotation process 68 computes CFG "weights" representing approximate execution costs associated with both nodes and arcs of the procedure body CFG and determines the sets of variables or parameters that must be passed to an emitted subgraph procedure or that must be promoted to static if the arc becomes a procedure call. Step 70 then assigns FALSE to a FailsMiserably flag to initialize it before beginning the Remove and Emit process 72, which analyzes the rejected procedure CFG to detect subgraphs that can be "emitted" as new procedure bodies and replaced with new procedure calls to reduce the rejected body. If the reduced procedure body is found to be more costly than the original rejected procedure body (by testing within process 72), then step 74 "fails miserably" and the procedure body reduction process 60 exits immediately without changing the rejected procedure body, col8, ln 15-55).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this eliminates the expensive portions of the original procedure body, the "reduced" procedure body is again passed to the in-line expansion process.
As to claim 6, Bates teaches the flags parameter is to indicate whether the dependency set is to replace an existing set( col8, ln 15-55) for the same reason as to claim 5 above.
As to claims 12, 13, 19, 20, they are rejected for the same reason as to claims 5-6 above.
12. Claims 7, 14 are rejected under 35 U.S.C. 103 as being unpatentable over
SANKARAN( US 20200401440 A1) in view of Kogelman( US 11573772 B2) in view of Manion( US 20040111469 A1 ) in view of Slesarenko( US 20160139894 A1) and further in view of LEBEANE( US 20200065255 A1).
As to claim 7, Lebeane teaches the one or more CUs are to share the L2 cache( a large L2 cache 112 is shared across all CUs 104 in a GPU 10, para[0007], ln 10-14)..
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this avoids accessing in-memory page tables on every memory access.
As to claims 14, it is rejected for the same reason as to claim 7 above.
Conclusion
US 11080026 B1 teaches the build module 104 may generate combined code including a third plurality of nodes by injecting the subgraph into the first plurality of nodes in place of the text-based node.
US 20100302261 A1 teaches All graphics calls made by an application that uses a fixed function pipeline are intercepted by a software component associated with the remote session. Those calls are then remapped to a shader pipeline. Some calls in the fixed function pipeline are identical to the shader pipeline, and thus do not need to be modified. Some calls in the fixed function pipeline have nearly equivalent calls in the shader pipeline, such as being identical, save for the name of the call. For those calls for which neither of the above two conversion methods apply, the drawing result that those calls will achieve is analyzed and a shader program that will cause the same drawing result is identified.
US 20160210721 A1 teaches The image graph implementation API provides function(s) for creating/adding nodes, for example: function. FIG. 1B illustrates a connection of nodes to create image processing tasks. The graph edges 111, 112, 113, 114 are provided by the image processing software developer to define the flow of the data array/data stream from source node 110 through the compute nodes 120, 130, 140, to destination node 150. The graph-based implementation API provides function(s) for connecting an image graph, for example:
US 20160210724 A1 teaches A graph class interface of a graph API enables adding nodes to a graph and connecting their input and output ports. Nodes of an image processing graph correspond to source and destination data and operations to be performed on images (image data blocks). FIG. 1A illustrates a set operations with each operation contained in a compute node (e.g., node 120, node 130, node 140) or source/destination node. Source node 110 and destination node 150 are each a data array or data stream entered into the graph explicitly. The image graph implementation API provides function(s) for creating/adding nodes, for example: [0038] // Create Nodes [0039] SrcNode:Params src1Params( ); [0040] Node
US 20210239477 A1 teaches an application programming interface (API) by TensorFlow™ can be used to construct the neural network model representative of a graph that includes nodes and edges. In this case, the model is mapped to underlying machine hardware. Nodes in the graph represent operations (e.g., machine learning functions, mathematical operations, etc.), and the edges represent the multidimensional data arrays also known as tensors communicated between the nodes.
US 9798527 B1 teaches IG. 5b illustrates an optimized version of the subgraph illustrated in FIG. 5a. The compilation system can use a pattern 525 of a library call that includes input arrays 502a, 502b, a transpose operation 515 and a dot operation to match patterns in the subgraph of FIG. 5a. After the compilation system matches the pattern 525 of the library call to the subgraph of 5a, the compilation system can fuse the subgraph into a single fusion library call operation. The compilation system can then replace the subgraph 5a in the computational graph with a fusion node 530 that represents the single fusion library call. During code generation, the compilation system translates the fusion node into the library call that performs all the fused operations to produce efficient compiled cod
US 20200401440 A1 ; and stateless user-defined compute functions using pre-defined APIs that read and update the graph data (as illustrated in the bottom portion of program code).
US 11080026 B1the build module 104 may generate combined code including a third plurality of nodes by injecting the subgraph into the first plurality of nodes in place of the text-based node. For examples, input edges to the text-based node may be redirected to serve as inputs to a node of the subgraph (e.g., the first node or function node) and input edges to the text-based node may be redirected to serve as output from a node of the subgraph (e.g., a last node or exit node of the subgraph). As with the injectable code 114, the combined code may be in the visual graph-based programming language or may be in an intermediate representation (e.g., node and pin).
US 20100302261 A1 teaches All graphics calls made by an application that uses a fixed function pipeline are intercepted by a software component associated with the remote session. Those calls are then remapped to a shader pipeline. Some calls in the fixed function pipeline are identical to the shader pipeline, and thus do not need to be modified. Some calls in the fixed function pipeline have nearly equivalent calls in the shader pipeline, such as being identical, save for the name of the call. For those calls for which neither of the above two conversion methods apply, the drawing result that those calls will achieve is analyzed and a shader program that will cause the same drawing result is identified.
US 20160210721 A1 teaches The image graph implementation API provides function(s) for creating/adding nodes, for example:
TABLE-US-00001 // Create Nodes SrcNode::Params src1Params( ); Node *in1=nfIA.CreateNode(SrcNode::NodeUniqueName( ), &src1Params); ... SimpleNode_2_1::Params simple1Params(idmAdd); Node *add=nfIA CreateNode(SimpleNode_2_1::NodeUniqueName( ), &simple1Params);objects contain information about node connectivity (number of input and output ports) and the main parameters for the function associated with the node. Objects of derivative classes can contain other parameters, depending on the node function. FIG. 1B illustrates a connection of nodes to create image processing tasks. The graph edges 111, 112, 113, 114 are provided by the image processing software developer to define the flow of the data array/data stream from source node 110 through the compute nodes 120, 130, 140, to destination node 150. The graph-based implementation API provides function(s) for connecting an image graph, for example: [0045] // Connect Graph [0046]
US 20210239477 A1 teaches an application programming interface (API) by TensorFlow™ can be used to construct the neural network model representative of a graph that includes nodes and edges. In this case, the model is mapped to underlying machine hardware. Nodes in the graph represent operations (e.g., machine learning functions, mathematical operations, etc.), and the edges represent the multidimensional data arrays also known as tensors communicated between the nodes. The unique edges, called control dependencies, can exist in the graph and denote that the source node must finish executing before the destination node starts executing. TensorFlow provides a platform in which the designer's design algorithm flow and computation architecture is automatically optimized. Nodes are assigned to computational devices and execute asynchronously, and in parallel once all the tensors on their incoming edges become available.
US 9798527 B1 teaches IG. 5b illustrates an optimized version of the subgraph illustrated in FIG. 5a. The compilation system can use a pattern 525 of a library call that includes input arrays 502a, 502b, a transpose operation 515 and a dot operation to match patterns in the subgraph of FIG. 5a. After the compilation system matches the pattern 525 of the library call to the subgraph of 5a, the compilation system can fuse the subgraph into a single fusion library call operation. The compilation system can then replace the subgraph 5a in the computational graph with a fusion node 530 that represents the single fusion library call. During code generation, the compilation system translates the fusion node into the library call that performs all the fused operations to produce efficient compiled code.
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/LECHI TRUONG/ Primary Examiner, Art Unit 2194
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