Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 7/9/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Priority
Applicant' s claim for the benefit of prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. The applicant' s claim for benefit of International Application No. PCT/CN2024/081206, filed on March 12, 2024 has been received and acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/30/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fastow et al. US 20200395328 A1 (hereinafter Fastow).
Regarding claim 1, Fastow discloses:
A semiconductor device, (Fig. 4, integrated memory structure 400) comprising:
semiconductor structures, (first memory array 404a and second memory array 404b) each of the semiconductor structures comprising a memory array ([0064], the array includes memory cells. See also Fig. 4.) and a first circuitry (See Fig. 4, everything other than memory cell. ) coupled to the memory array; (See Fig. 4.) and
at least one control structure (logic circuitry 408) comprising second circuitries (logic components 418a-c) for the semiconductor structures, wherein each of the second circuitries is coupled to a memory array of a respective semiconductor structure of the semiconductor structures, (See Fig. 4.) wherein the semiconductor structures and the at least one control structure are stacked together along a direction. (See Fig. 4, memory arrays 404a, 404b and logic circuitry 408 are stacked in the vertical direction.)
Regarding claim 2, Fastow further discloses:
wherein the at least one control structure(logic circuitry 408) comprises two or more control structures (logic component 418a and 418b) that are connected together to an external device.([0066], interconnect terminals 402 connect the device to external devices.)
Regarding claim 3, Fastow further discloses:
wherein the semiconductor structures (Fig. 4, memory array 404a and 404b) comprise a first semiconductor structure (memory array 404b) having a first bonding layer (bonding interface 410b) and a second semiconductor structure (memory array 404a) having a second bonding layer, (bonding interface 410a)
wherein the at least one control structure (logic circuitry 408) comprises a control structure having a third bonding layer ([0061] along with Fig 3A-B hybrid bonding where the logic circuit having layer 211b surface 201b which faces away from the logic circuitry 208/408) and a fourth bonding layer, (bonding layer the opposite surface having second layer 211b on the faces away from the logic circuity 208/408) the third bonding layer being in a first side of the control structure, (side facing memory array 404b) the fourth bonding layer being in a second side of the control structure that is opposite to the first side of the control structure along the direction, (side facing memory array 404a) and
wherein the first semiconductor structure (memory array 404b) and the second semiconductor structure (memory array 404a) are integrated on opposite sides of the control structure (logic circuit 408) (See also Fig. 4), with the first bonding layer being in contact with the third bonding layer and the second bonding layer being in contact with the fourth bonding layer. (See Fig. 3B, the third bonding layer would be in contact with the first bonding layer and the fourth bonding layer would be in contact with the second bonding layer.)
Regarding claim 4, Fastow further discloses:
wherein a first circuitry of the first semiconductor structure (See Fig. 4, everything other than memory cell in memory array 404b) and the first bonding layer(memory array 404b) are in a first side of the first semiconductor structure, (See Fig. 4)
wherein a first circuitry of the second semiconductor structure (See Fig. 4, everything other than memory cell in memory array 404a) and the second bonding layer (bonding layer 410a) are in a first side of the second semiconductor structure, (See Fig. 4) and
wherein the control structure (logic circuitry 408) comprises a first peripheral circuitry (logic components 418a) and a second peripheral circuitry (logic components 418b) in the first side of the control structure, (See Fig. 4) and the first peripheral circuitry is connected to a first memory array of the first semiconductor structure (logic component connected at least by interconnects 415. See also [0071]-[0072].) and the second peripheral circuitry is connected to a second memory array of the second semiconductor structure. (logic component connected at least by interconnects 415. See also [0071]-[0072].)
Regarding claim 5, Fastow further discloses:
a first conductive interconnection structure (interconnect structures 415) on the second side of the control structure, (See Fig. 4 interconnects structures on the second side of the logic circuitry 408.) wherein the first peripheral circuitry (logic components 418a) and the second peripheral circuitry (logic components 418b) are respectively connected to the first conductive interconnection structure; (interconnect structures 415) and
a second conductive interconnection structure (interconnect structure 411) on a second side of the second semiconductor structure that is opposite to the first side of the second semiconductor structure along the direction, (See Fig. 4)
wherein the first circuitry of the first semiconductor structure (everything other than memory cell within the memory array 404b) is connected to the first peripheral circuitry (logic components 418a) at least by a first conductive structure (interconnect structure 415) coupled between the first circuitry of the first semiconductor structure and the first conductive interconnection structure, (See Fig. 4) the first conductive structure extending through the first bonding layer, the third bonding layer, and the control structure along the direction, and (See Fig. 4 and Figs. 3A-3B)
wherein the first circuitry of the second semiconductor structure (everything other than memory cell within the memory array 404a) is connected to the second peripheral circuitry (logic components 418b) at least by a second conductive structure (interconnect structure 413) coupled between the first circuitry of the second semiconductor structure and the second conductive interconnection (interconnect structures 411) structure and a third conductive structure (interconnect structure 413) coupled between the second conductive interconnection structure (interconnect structures 411)and the first conductive interconnection structure, (interconnect structures 415) (See Fig. 4) the second conductive structure extending at least partially through the second semiconductor structure along the direction, (See Fig. 4) the third conductive structure extending through the second semiconductor structure, the second bonding layer, and the fourth bonding layer along the direction. (See Fig. 4 and Figs. 3A-3B.)
Regarding claim 6, Fastow further discloses:
first bonding layer (bonding interface 410b/311a) comprises one or more first conductive contacts (Fig. 3A interconnect structure 319a in the memory array 404b area) isolated by a first dielectric material, ([0055], layer 311a is SiO2.) the second bonding layer (bonding interface 410a/311a) comprises one or more second conductive contacts (interconnection structure 319a with in a memory array 404a area) isolated by a second dielectric material, ([0055], layer 311a is SiO2.) the third bonding layer (bonding interface layer 311b) comprises one or more third conductive contacts(Fig. 3A interconnect structure 319b in the logic circuitry 408 area) isolated by a third dielectric material, ([0055], layer 311b is SiO2.) and the fourth bonding layer (Fig. 3A interconnect structure 319b in the logic circuitry 408 area opposite the third bonding layer) comprises one or more fourth conductive contacts isolated by a fourth dielectric material, ([0055], layer 311a is SiO2.) and
wherein at least one of the one or more first conductive contacts is in contact with a corresponding one of the one or more third conductive contacts, and at least one of the one or more second conductive contacts is in contact with a corresponding one of the one or more fourth conductive contacts. (See Fig. 3B, the third bonding layer would be in contact with the first bonding layer and the fourth bonding layer would be in contact with the second bonding layer.)
Regarding claim 7, Fastow further discloses:
a conductive interconnection structure (interconnect structure 411) on a second side of the first semiconductor structure (memory array 404b) that is opposite to the first side of the first semiconductor structure along the direction, (See Fig. 4)
wherein the first peripheral circuitry (logic components 418a) is connected to the conductive interconnection structure(interconnect structure 411) by a first conductive structure (interconnect structure 413 and interconnect structure 320) extending in the first semiconductor structure, (See Fig. 4, the logic components 418a is connected by interconnects on the same device) a first conductive contact (interconnect structure 319a) of the one or more first conductive contacts, (interconnect structure 320 including interconnect structure 319aand 319b) and a corresponding third conductive contact (interconnect structure 319b) of the one or more third conductive contacts that is in contact with the first conductive contact, (interconnect structure 319a) (See Fig. 4 and 3B)
wherein the first circuitry of the first semiconductor structure (See Fig. 4, everything other than memory cell in memory array 404b.) is connected to the first peripheral circuitry (logic components 418a) by one or more other first conductive contacts (interconnect structure 319a/411) being in contact with corresponding one or more other third conductive contacts, and (See Fig. 4)
wherein the first circuitry of the second semiconductor structure (See Fig. 4, everything other than memory cell in memory array 404a.) is connected to the second peripheral circuitry (logic components 418b) by the at least one of the one or more second conductive contacts, the corresponding one of the one or more fourth conductive contacts, and a second conductive structure at least partially extending through the control structure. (See Fig. 4)
Regarding claim 14, Fastow discloses all of the elements of claim 1.
Fastow further discloses:
wherein the first circuitry (See Fig. 4, everything other than memory cell. ) comprises at least one of a sense amplifier coupled to a corresponding bit line or a word line driver ([0071] the logic circuitry includes word line drivers) coupled to a corresponding word line (worldlines 420) (The examiner understands the purpose of a word line driver is to drive a signal to the wordline and therefore would be coupled to the wordline in the first circuitry) , and
wherein the second circuitry comprises an input-output (I/O) circuitry configured to communicate with one or more external devices. (Interconnect 402 is connected to the logic circuitry through the top surface of the memory array 404a therefore the logic circuitry 408 is configured to communicate with one or more external devics.)
Regarding claim 19, Fastow discloses:
A method for forming a semiconductor device, the method comprising:
providing semiconductor structures, (first memory array 404a and second memory array 404b) each of the semiconductor structures comprising a memory array ([0064], the array includes memory cells. See also Fig. 4.) and a first circuitry (See Fig. 4, everything other than memory cell. ) coupled to the memory array; (See Fig. 4.)
providing at least one control structure (logic circuitry 408) comprising second circuitries; (logic components 418a-c) and
stacking the semiconductor structures on the at least one control structure along a direction and connecting each of the second circuitries to a memory array of a respective semiconductor structure of the semiconductor structures. . (See Fig. 4, memory arrays 404a, 404b and logic circuitry 408 are stacked in the vertical direction.)
Regarding claim 20, Fastow further discloses:
wherein stacking the semiconductor structures (See Fig. 4, memory arrays 404a, 404b and logic circuitry 408 are stacked in the vertical direction.)on the at least one control structure (logic circuitry 408) comprises at least one of:
stacking semiconductor structures on opposite sides of a control structure of the at least one control structure along the direction, (See Fig. 4, the memory arrays 404a and 404b are stacked on opposite sides of the logic circuitry 408. ) or
stacking semiconductor structures on a same side of a control structure of the at least one control structure along the direction.
In the alternative, claims 1, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishikawa et al. US 20200266182 A1 (hereinafter Nishikawa)
Regarding claim 1, Nishikawa discloses:
A semiconductor device, (Fig. 23, memory structure) comprising:
semiconductor structures, (memory die 900A and 900B) each of the semiconductor structures comprising a memory array (the first-tier structure (132, 142, 170, 165) of 900A and 900B) and a first circuitry (See Fig. 4, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) coupled to the memory array; (See Fig. 23) and
at least one control structure (support die 700) comprising second circuitries (peripheral circuitry 710) for the semiconductor structures, wherein each of the second circuitries is coupled to a memory array of a respective semiconductor structure of the semiconductor structures, (See Fig. 23, interconnect structures 780)
wherein the semiconductor structures and the at least one control structure are stacked together along a direction. (See Fig. 23)
Regarding claim 19, Nishikawa
A method for forming a semiconductor device, (Fig. 23, memory structure) the method comprising:
providing semiconductor structures, (first memory die 900A and 900B) each of the semiconductor structures comprising a memory array (the first-tier structure (132, 142, 170, 165) and a first circuitry (See Fig. 4, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) coupled to the memory array; (See Fig. 23)
providing at least one control structure (support die 700) comprising second circuitries; (peripheral circuitry 710) and
stacking the semiconductor structures on the at least one control structure along a direction and connecting each of the second circuitries to a memory array of a respective semiconductor structure of the semiconductor structures. (See Fig. 23)
Regarding claim 20, Nishikawa further discloses:
stacking the semiconductor structures (first memory die 900A and 900B) on the at least one control structure (support die 700) comprises at least one of:
stacking semiconductor structures on opposite sides of a control structure of the at least one control structure along the direction, or
stacking semiconductor structures on a same side of a control structure of the at least one control structure along the direction. (See Fig. 23)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa further in view of Fastow.
Regarding claim 8, Nishikawa discloses all the elements of claim 1.
wherein the at least one control structure (support die 700) …
wherein the semiconductor structures comprise a first semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900A) and a second semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900B)that are stacked … along the direction, (See Fig. 23)
wherein the first semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900A) …
wherein the second semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900B) …
While Nishikawa discloses that the memory die 900A is bonded to the support die 700 and the memory die 900B, Nishikawa does not appear to specifically disclose “a first boding layer”, “a second bonding layer in a first side of the first side of the first semiconductor structure” , “a third bonding layer in a second side of the first semiconductor structure that is opposite to the first side of the first semiconductor structure”, and “a fourth bonding layer”.
Fastow, which teaches bonding between logic and bonded to a memory array (Fastow, Abstract). Fastow discloses Fig 3A-B hybrid bonding between two devices/surfaces that could be done at the top surface of a device surface (layer 311b) or a bottom surface of a device surface (layer 311a).
The combination of Nishikawa and Fastow would have been obvious to one of ordinary skill in the art before the effective filing date to result in the claimed device including “a first boding layer”, “a second bonding layer in a first side of the "first side of the first semiconductor structure” , “a third bonding layer in a second side of the first semiconductor structure that is opposite to the first side of the first semiconductor structure”, and “a fourth bonding layer” where “the first semiconductor structure is stacked on the first control structure with the first bonding layer being in contact with the second bonding layer, and the second semiconductor structure is stacked on the first semiconductor structure with the fourth bonding layer being in contact with the third bonding layer”. The combination of Nishikawa and Fastow would be predictable.
Regarding claim 9, Nishikawa and Fastow disclose all the elements of claim 8.
Nishkawa further discloses:
wherein a first circuitry (See Fig. 23, via structures 88, bit lines 98, and interconnection line structures 96) of the first semiconductor structure (memory die 900A) … the first side of the first semiconductor structure, (See Fig. 23)
wherein a first circuitry (See Fig. 23, via structures 88, bit lines 98, and interconnection line structures 96.) of the second semiconductor structure (memory die 900B) … first side of the second semiconductor structure, (See Fig. 23)
wherein the first control structure (support die 700) comprises a first peripheral circuitry ([0139], CMOS devices within the peripheral circuity 710) and a second peripheral circuitry ([0139], CMOS devices within the peripheral circuity 710) in the first side of the first control structure, (See Fig. 23) and wherein the first peripheral circuitry (support die 700) is connected to a first memory array of the first semiconductor structure, (memory die 900A) and the second peripheral circuitry is connected to a second memory array of the second semiconductor structure. (memory die 900B) (See Fig. 23)
The combination of Nishikawa and Fastow would by necessity have “the second bonding layer are in the first side of the first semiconductor structure” and “the fourth bonding layer are in a first side of the second semiconductor structure.”
Regarding claim 10, Nishikawa and Fastow disclose all the elements of claim 8.
Nishikawa further disclose:
a first conductive interconnection (Fig. 23 bonding pad 688B) structure on the second side of the first semiconductor structure, (memory die 900A) the first conductive interconnection structure being connected to the first circuitry (See Fig. 4, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) of the first semiconductor structure; (memory 900A) and (See Fig. 23)
a second conductive interconnection (bonding pad 888B) structure on a second side of the second semiconductor structure (memory die 900B) that is opposite to the first side of the second semiconductor structure along the direction, (See Fig. 23) the second conductive interconnection structure being connected to the first circuitry (See Fig. 4, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) of the second semiconductor structure (memory die 900B), (See Fig. 23)
wherein the first circuitry (See Fig. 23, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) of the first semiconductor structure (memory die 900A) is connected to the first peripheral circuitry ([0139], CMOS devices within the peripheral circuity 710) at least by a first conductive structure (interconnect 780) coupled between the first conductive interconnection (bonding pads 988B) structure and the first peripheral circuitry,( support die 700) the first conductive structure extending at least partially through the first semiconductor structure along the direction, and (See Fig. 23)
wherein the first circuitry(See Fig. 23, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) of of the second semiconductor structure (memory die 900B) is connected to the second peripheral circuitry ([0139], CMOS devices within the peripheral circuity 710) at least by a second conductive structure (structure made by through die structures including 488/588/96 and 980) coupled between the second conductive interconnection (bonding pad 888C) structure and the second peripheral circuitry, (bonding pad 788C) the second conductive structure extending through at least partially through the second semiconductor structure and at least partially through the first semiconductor structure along the direction. (See Fig. 23)
Regarding claim 11, Nishikawa and Fastow disclose all the elements of claim 8.
the at least one control structure (support die 700 includes CMOS devices within the peripheral circuity 710) comprises a second control structure (support die 700 includes CMOS devices within the peripheral circuity 710) comprises, and wherein the semiconductor structures (memory die 900A) comprise a first plurality of semiconductor structures including the first semiconductor structure and the second semiconductor structure and a second plurality of semiconductor structures, (See Fig. 23, structures 58 within the memory-level assembly.)
wherein the first plurality of semiconductor structures are stacked on the first side of the first control structure, and (See Fig. 23)
wherein the first plurality of semiconductor structures and the second semiconductor structures are stacked on opposite sides of the second control structure along the direction. (See Fig. 23)
Regarding claim 12, Nishikawa and Fastow disclose all the elements of claim 11.
the first control structure ([0139], CMOS devices within the peripheral circuity 710) comprises a first plurality of second circuitries respectively coupled to first circuitries in the first plurality of semiconductor structures, and (See Fig. 23)
wherein the second control structure ([0139], CMOS devices within the peripheral circuity 710) comprises a second plurality of second circuitries respectively coupled to first circuitries in the second plurality of semiconductor structures. (See Fig. 23)
Claims 13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Fastow in view of Zhu et al. US 20230060149 A1 (hereinafter Zhu).
Regarding claim 13, Fastow discloses all the elements of claim 1,
Fastow discloses a 3D memory as the memory array.
Fastow does not specifically disclose:
wherein a memory cell of the memory array comprises a transistor and a capacitor,
wherein the transistor comprises a gate as at least part of a word line, a first terminal coupled to a bit line, and a second terminal coupled to the capacitor, and
wherein the bit line and the capacitor are on a same side of the word line.
Zhu, teaches a 3D memory device with vertical bonding to a peripheral circuit (Zhu, Abstract), discloses:
wherein a memory cell (Fig. 3, DRAM cell 302) of the memory array (memory cell array 201) comprises a transistor (transistor 304) and a capacitor (capacitor 306),
wherein the transistor comprises a gate as at least part of a word line, , (See Fig. 3, the transistor 304 has a gate which is connected to the word line 204) a first terminal coupled to a bit line, (a terminal of the transistor 304 is connected to the bit line 206) and a second terminal coupled to the capacitor, (the second terminal of the transistor 304 is connected to the capacitor 306) and
wherein the bit line and the capacitor are on a same side of the word line. (See Fig. 3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Fastow to have a memory cell of the memory array comprises a transistor and a capacitor, wherein the transistor comprises a gate as at least part of a word line, a first terminal coupled to a bit line, and a second terminal coupled to the capacitor, and wherein the bit line and the capacitor are on a same side of the word line as taught by Zhu for purposes of reducing the area occupied by the memory array ([0062]).
Regarding claim 15, Fastow discloses:
A semiconductor device,(Fig. 4, integrated memory structure 400) comprising:
semiconductor structures, (first memory array 404a and second memory array 404b) each of the semiconductor structures comprising a memory array ([0064], the array includes memory cells. See also Fig. 4.) and a first circuitry (See Fig. 4, everything other than memory cell. ) coupled to the memory array; (See Fig. 4.) and
at least one control structure (logic circuitry 408) comprising second circuitries (logic components 418a-c) for the semiconductor structures, wherein the semiconductor structures and the at least one control structure are stacked together along a direction, (See Fig. 4, memory arrays 404a, 404b and logic circuitry 408 are stacked in the vertical direction.) and
Fastow does not appear to specifically disclose:
wherein a memory cell of the memory array comprises a transistor and a capacitor, wherein the transistor comprises a gate as at least part of a word line, a first terminal coupled to a bit line, and a second terminal coupled to the capacitor, and wherein the bit line and the capacitor are on a same side of the word line.
Zhu, which teaches a three-dimensional (3D) memory device, discloses:
wherein a memory cell (Fig. 3, DRAM cell 302) of the memory array (memory cell array 201) comprises a transistor (transistor 304) and a capacitor (capacitor 306), wherein the transistor comprises a gate as at least part of a word line, (See Fig. 3, the transistor 304 has a gate which is connected to the word line 204) a first terminal coupled to a bit line, (a terminal of the transistor 304 is connected to the bit line 206) and a second terminal coupled to the capacitor, (the second terminal of the transistor 304 is connected to the capacitor 306) and wherein the bit line (bit line 206) and the capacitor (capacitor 306) are on a same side of the word line.(See Fig. 3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Fastow to have a memory cell of the memory array comprises a transistor and a capacitor, wherein the transistor comprises a gate as at least part of a word line, a first terminal coupled to a bit line, and a second terminal coupled to the capacitor, and wherein the bit line and the capacitor are on a same side of the word line as taught by Zhu for purposes of reducing the area occupied by the memory array ([0062]).
Regarding claim 16, Fastow and Zhu disclose all the elements of claim 15.
Fastow further discloses:
wherein the semiconductor structures (Fig. 4, memory array 404a and 404b) comprise a first semiconductor structure (memory array 404b) having a first bonding layer (bonding interface 410b) and a second semiconductor structure (memory array 404a) having a second bonding layer, (bonding interface 410a)
wherein the at least one control structure (logic circuitry 408) comprises a control structure having a third bonding layer ([0061] along with Fig 3A-B hybrid bonding where the logic circuit having layer 211b surface 201b which faces away from the logic circuitry 208/408) and a fourth bonding layer, (bonding layer the opposite surface having second layer 211b on the faces away from the logic circuity 208/408) the third bonding layer being in a first side of the control structure, (side facing memory array 404b) the fourth bonding layer being in a second side of the control structure that is opposite to the first side of the control structure along the direction, (side facing memory array 404a) and
wherein the first semiconductor structure (memory array 404b) and the second semiconductor structure (memory array 404a) are integrated on opposite sides of the control structure (logic circuit 408) (See also Fig. 4), with the first bonding layer being in contact with the third bonding layer and the second bonding layer being in contact with the fourth bonding layer, (See Fig. 3B, the third bonding layer would be in contact with the first bonding layer and the fourth bonding layer would be in contact with the second bonding layer.) and
wherein a first circuitry of the first semiconductor structure (See Fig. 4, everything other than memory cell in memory array 404b) and the first bonding layer(memory array 404b) are in a first side of the first semiconductor structure, (See Fig. 4)
wherein a first circuitry of the second semiconductor structure (See Fig. 4, everything other than memory cell in memory array 404a) and the second bonding layer (bonding layer 410a) are in a first side of the second semiconductor structure, (See Fig. 4) and
wherein the control structure (logic circuitry 408) comprises a first peripheral circuitry (logic components 418a) and a second peripheral circuitry (logic components 418b) in the first side of the control structure, (See Fig. 4) and the first peripheral circuitry is connected to a first memory array of the first semiconductor structure (logic component connected at least by interconnects 415. See also [0071]-[0072].) and the second peripheral circuitry is connected to a second memory array of the second semiconductor structure. (logic component connected at least by interconnects 415. See also [0071]-[0072].)
Regarding claim 17, Fastow and Zhu disclose all the elements of claim 16.
Fastow further discloses:
first bonding layer (bonding interface 410b/311a) comprises one or more first conductive contacts (Fig. 3A interconnect structure 319a in the memory array 404b area) isolated by a first dielectric material, ([0055], layer 311a is SiO2.) the second bonding layer (bonding interface 410a/311a) comprises one or more second conductive contacts (interconnection structure 319a with in a memory array 404a area) isolated by a second dielectric material, ([0055], layer 311a is SiO2.) the third bonding layer (bonding interface layer 311b) comprises one or more third conductive contacts(Fig. 3A interconnect structure 319b in the logic circuitry 408 area) isolated by a third dielectric material, ([0055], layer 311b is SiO2.) and the fourth bonding layer (Fig. 3A interconnect structure 319b in the logic circuitry 408 area opposite the third bonding layer) comprises one or more fourth conductive contacts isolated by a fourth dielectric material, ([0055], layer 311a is SiO2.) and
wherein at least one of the one or more first conductive contacts is in contact with a corresponding one of the one or more third conductive contacts, and at least one of the one or more second conductive contacts is in contact with a corresponding one of the one or more fourth conductive contacts. (See Fig. 3B, the third bonding layer would be in contact with the first bonding layer and the fourth bonding layer would be in contact with the second bonding layer.)
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa and Zhu.
Regarding claim 15,
A semiconductor device, (Fig. 23, memory structure) comprising:
semiconductor structures, (memory die 900A and 900B) each of the semiconductor structures comprising a memory array (the first-tier structure (132, 142, 170, 165) of 900A and 900B) and a first circuitry (See Fig. 4, everything other than memory cell including via structures 88, bit lines 98 and interconnection line structures 96) coupled to the memory array; (See Fig. 23) and
at least one control structure (support die 700) comprising second circuitries (peripheral circuitry 710) for the semiconductor structures, wherein each of the second circuitries is coupled to a memory array of a respective semiconductor structure of the semiconductor structures, (See Fig. 23, interconnect structures 780)
wherein the semiconductor structures and the at least one control structure are stacked together along a direction, (See Fig. 23)
Nishikawa discloses a three-dimensional memory device including a three-dimensional array of memory elements and peripheral circuitry (Nishikawa, [0041]). However, Nishikawa does directly disclose:
wherein a memory cell of the memory array comprises a transistor and a capacitor, wherein the transistor comprises a gate as at least part of a word line, a first terminal coupled to a bit line, and a second terminal coupled to the capacitor, and
wherein the bit line and the capacitor are on a same side of the word line.
Zhu, teaches a 3D memory device with vertical bonding to a peripheral circuit (Zhu, Abstract), discloses:
wherein a memory cell (Fig. 3, DRAM cell 302) of the memory array (memory cell array 201) comprises a transistor (transistor 304) and a capacitor (capacitor 306),
wherein the transistor comprises a gate as at least part of a word line, , (See Fig. 3, the transistor 304 has a gate which is connected to the word line 204) a first terminal coupled to a bit line, (a terminal of the transistor 304 is connected to the bit line 206) and a second terminal coupled to the capacitor, (the second terminal of the transistor 304 is connected to the capacitor 306) and
wherein the bit line and the capacitor are on a same side of the word line. (See Fig. 3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nishikawa to have a memory cell of the memory array comprises a transistor and a capacitor, wherein the transistor comprises a gate as at least part of a word line, a first terminal coupled to a bit line, and a second terminal coupled to the capacitor, and wherein the bit line and the capacitor are on a same side of the word line as taught by Zhu for purposes of reducing the area occupied by the memory array ([0062]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa and Zhu as applied to claim 15 above, and further in view of Fastow.
Regarding claim 18, Fastow and Zhu disclose all the elements of claim 15.
wherein the at least one control structure (support die 700) …
wherein the semiconductor structures comprise a first semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900A) and a second semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900B)that are stacked … along the direction, (See Fig. 23)
wherein the first semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900A) …
wherein the second semiconductor structure (the first-tier structure (132, 142, 170, 165) of 900B) …
… and
wherein a first circuitry (See Fig. 23, via structures 88, bit lines 98, and interconnection line structures 96) of the first semiconductor structure (memory die 900A) … the first side of the first semiconductor structure, (See Fig. 23)
wherein a first circuitry (See Fig. 23, via structures 88, bit lines 98, and interconnection line structures 96.) of the second semiconductor structure (memory die 900B) … first side of the second semiconductor structure, (See Fig. 23)
wherein the first control structure (support die 700) comprises a first peripheral circuitry ([0139], CMOS devices within the peripheral circuity 710) and a second peripheral circuitry ([0139], CMOS devices within the peripheral circuity 710) in the first side of the first control structure, (See Fig. 23) and wherein the first peripheral circuitry (support die 700) is connected to a first memory array of the first semiconductor structure, (memory die 900A) and the second peripheral circuitry is connected to a second memory array of the second semiconductor structure. (memory die 900B) (See Fig. 23)
While Nishikawa discloses that the memory die 900A is bonded to the support die 700 and the memory die 900B, Nishikawa does not appear to specifically disclose “a first boding layer”, “a second bonding layer in a first side of the first side of the first semiconductor structure” , “a third bonding layer in a second side of the first semiconductor structure that is opposite to the first side of the first semiconductor structure”, and “a fourth bonding layer”.
Fastow, which teaches bonding between logic and bonded to a memory array (Fastow, Abstract). Fastow discloses Fig 3A-B hybrid bonding between two devices/surfaces that could be done at the top surface of a device surface (layer 311b) or a bottom surface of a device surface (layer 311a).
The combination of Nishikawa, Zhu and Fastow would have been obvious to one of ordinary skill in the art before the effective filing date to result in the claimed device including “a first boding layer”, “a second bonding layer in a first side of the "first side of the first semiconductor structure” , “a third bonding layer in a second side of the first semiconductor structure that is opposite to the first side of the first semiconductor structure”, and “a fourth bonding layer” where “the first semiconductor structure is stacked on the first control structure with the first bonding layer being in contact with the second bonding layer, and the second semiconductor structure is stacked on the first semiconductor structure with the fourth bonding layer being in contact with the third bonding layer” and “the second bonding layer are in the first side of the first semiconductor structure” and “the fourth bonding layer are in a first side of the second semiconductor structure. The combination of Nishikawa and Fastow would be predictable.
Prior Art Considered Pertinent
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou et al. US 10665581 B1 – Fig. 21A and 21B support die 700 between memory die 900A and 900B.
Yada et al US 20200227397 A1 – Fig. 23 support die 700 with memory die 900A and 900B over the support die.
Theil US 20230197496 A1 – bonding method for bonding two semiconductor elements directly.
Chuang US 20230352317 A1 – Fig. 14 logic wafer 20 is bonded with multiple chips C over the logic wafer.
Zhang et al. US 20240215272 A1 - Figs. 1A-1H shows multiple different examples of organizing the stack such having the memory arrays on top a peripheral circuit or having the peripheral circuits between the memory arrays.
Conclusion
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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