DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. Patent No. US 11,804,708.
Regarding claims 1, 10, Chen discloses an electrostatic discharge (ESD) protection circuit comprising:
a clamp circuit coupled between a first voltage supply node [Fig. 4, ground 306] and a second voltage supply node [Fig. 4, I/O pad],
the clamp circuit including:
a first transistor [Fig. 4, transistor 416] having a first current electrode, a second current electrode coupled at the second voltage supply node [Fig. 4, source of 416 coupled to ground], and a control electrode [Fig. 4, gate electrode] coupled to the second voltage supply node by way of a first resistor;
a second transistor [Fig. 4, transistor 412] coupled in series with the first transistor, the second transistor having a first current electrode coupled at the first voltage supply node, a second current electrode, and a control electrode;
a first bias generator circuit [Fig. 4, gate bias circuit 310 comprising voltage level shifter 408] coupled at the control electrode of the second transistor, the first bias generator circuit configured to cause a gate-to-source voltage of the second transistor to be substantially equal to a gate-to-source voltage of the first transistor during a normal operating mode [col. 6 lines 66 to col. 7 lines 15]; and
a trigger circuit [Fig. 4, inverter 410] coupled with the clamp circuit, the trigger circuit having a first output coupled at the control electrode of the first transistor and a second output coupled at the control electrode of the second transistor [col. 7 lines 15 – 32].
Allowable Subject Matter
Claims 2-9, 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claim 2: The prior art does not disclose that the first bias generator circuit comprises a second resistor having a first terminal coupled at the control electrode of the second transistor and a second terminal coupled at the second current electrode of the second transistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claims 3, 11: The prior art does not disclose that the clamp circuit further includes a third transistor coupled in series between the first transistor and the second transistor, the third transistor having a first current electrode coupled at the second current electrode of the second transistor, a second current electrode coupled at the first current electrode of the first transistor, and a control electrode. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claims 5, 13: The prior art does not disclose a second inverter stage including: a third trigger transistor having a first current electrode coupled at the second output of the trigger circuit, a second current electrode coupled at the third voltage supply node, a control electrode coupled at the first trigger node. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
The following is an examiner’s statement of reasons for allowance of claims 7, 15: The prior art does not further comprise a voltage divider circuit coupled with the trigger circuit, the voltage divider circuit having a first tap and configured to generate a first reference voltage at the first tap. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Claims 16-20 are allowed.
The prior art does not disclose an electrostatic discharge (ESD) protection circuit comprising:
a clamp circuit coupled between a first voltage supply node and a second voltage supply node, the clamp circuit including: a third transistor having a first current electrode coupled at the first voltage supply node, a second current electrode coupled at the first current electrode of the second transistor at a second clamp node, a control electrode, and a body electrode coupled at the second current electrode; a second bias generator circuit coupled at the control electrode of the third transistor; and a trigger circuit coupled with the clamp circuit, the trigger circuit having a first output coupled at the control electrode of the first transistor, a second output coupled at the control electrode of the second transistor, and a third output coupled at the control electrode of the third transistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838
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