DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/10/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 2-3 are objected to because of the following informalities:
Claim 2, line 2: “0,1 µm” should read --- 0.1 µm ---
Claim 3, line 2: “0,1 µm” should read --- 0.1 µm ---
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the highly doped layer" in line 1. There is insufficient antecedent basis for this limitation in the claim. There is no prior recitation of “a highly doped layer” in claim 16, or claim 13 on which claim 16 depends, or claim 1 on which claim 13 depends, rendering it unclear what “the highly doped layer” refers to in claim 16. Therefore, for the purposes of Examination, Examiner has interpreted “the highly doped layer” in claim 16 as --- the interruption layer --- however, this edit may be altered if Applicant intends otherwise.
Claim 16 recites the limitation "the buffer layer" in line 2. There is insufficient antecedent basis for this limitation in the claim. There is no prior recitation of “a buffer layer” in claim 16, or claim 13 on which claim 16 depends, or claim 1 on which claim 13 depends, rendering it unclear what “the buffer layer” refers to in claim 16, line 2. Therefore, for the purposes of Examination, Examiner has interpreted “the buffer layer” in claim 16, line 2 as --- a buffer layer --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 8-11, 13-15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishibashi (U.S. PG Pub No US2013/0092956A1).
Regarding claim 1, Ishibashi teaches a semiconductor die (300) fig. 7 [0105] (obtained by dicing [0123]), comprising:
a semiconductor device (DiMOSFET comprising 124-125) fig. 7 [0105] in a semiconductor body (100 with 120) fig. 7 [0105-0109] (100 and 120 being formed of doped semiconductor(s) [0105-0109],
the semiconductor body (100 with 120) comprising:
a silicon carbide substrate (10 and 1 of substrate 100) fig. 7 [0106] (1, 10 formed of silicon carbide) [0112];
an epitaxial silicon carbide layer system (121-123 of 120) fig. 7 [0105-0109] on a first side (top of 1) of the silicon carbide substrate (10 and 1); and
an interruption layer (11) fig. 7 [0106];
wherein the interruption layer (11) is at least one of:
embedded (vertically embedded) into the silicon carbide substrate (10 and 1) at a vertical distance (non-zero thickness of 1) from the first side (top of 1) of the silicon carbide substrate (10 and 1 of 100) [0105].
Regarding claim 5, Ishibashi teaches the semiconductor die (300) fig. 7 [0105] of claim 1. Ishibashi also teaches wherein the interruption layer (11) fig. 7 [0106] is at least one of an amorphous layer [0016, 0061] and/or a porous layer [0058] (connection layer 11 may be both amorphous [0016] and provided with substantial degree of porosity [0013]).
Regarding claim 8, Ishibashi teaches the semiconductor die (300) fig. 7 [0105] of claim 5. Ishibashi also teaches wherein at least one of the amorphous layer (11) fig. 7 [0016, 0061, 0106] and/or the porous layer (11) [0013, 0058] is embedded into the silicon carbide substrate (vertically embedded) into the silicon carbide substrate (10 and 1 of 100) fig. 7 [0105-0106].
Regarding claim 9, Ishibashi teaches the semiconductor die (300) fig. 7 [0105] of claim 1. Ishibashi also teaches comprising a metallization layer (112) fig. 7 [0105-0106] (electrode [0106] metal such as nickel [0122-0124]) arranged on a second side (bottom of 10) fig. 7 [0106] of the silicon carbide substrate (100) [0112] vertically opposite to the first side (top of 1).
Regarding claim 10, Ishibashi teaches the semiconductor die (300) fig. 7 [0105] of claim 1. Ishibashi also teaches wherein the semiconductor device (DiMOSFET comprising 124-125) fig. 7 [0105] is a vertical transistor device (vertical DiMOSFET) [0105] having a source region (comprising 111) fig. 7 [0105] and a drain region (comprising 112) fig. 7 [0105] at opposite (top/bottom) sides of the semiconductor body (100 with 120) fig. 7 [0105-0109].
Regarding claim 11, Ishibashi teaches the semiconductor die (300) fig. 7 [0105] of claim 1. Ishibashi also teaches comprising an additional interruption layer (126) fig. 7 [0109-0110] (interrupting connection between 110 and 120) which is vertically spaced apart from the interruption layer (11) fig. 7 [0106].
Regarding claim 13, Ishibashi teaches a method of manufacturing [see fig. 8, 0111] the semiconductor die (300) fig. 7 [0105] of claim 1, comprising:
providing [see fig. 8, 0112] the silicon carbide substrate (10 and 1 of substrate 100) fig. 7 [0106];
epitaxially depositing [see figs. 9-10, 0114-0115] the epitaxial silicon carbide layer system (121-123 of 120) fig. 7 [0105-0109] on the first side (top of 1) of the silicon carbide substrate (10 and 1); and
forming [see fig. 9, 0112] the interruption layer (11) fig. 7 [0106].
Regarding claim 14, Ishibashi teaches the method [see fig. 8, 0111] of claim 13. Ishibashi also teaches wherein the interruption layer (11) fig. 7 [0106] is formed by at least one of a porosification (porosity adjustment of layer 11 [0058, 0130-0132] performed) (see also fig. 6, 0102-0104].
Regarding claim 15, Ishibashi teaches the method [see fig. 8, 0111] of claim 14. Ishibashi also teaches wherein forming the interruption layer (11) fig. 7 [0106] is performed (in S110 [see fig. 8, 0112]) prior to (in S120 [see fig. 8, 0113]) epitaxially depositing [see figs. 9-10, 0114-0115] the epitaxial silicon carbide layer system (121-123 of 120) fig. 7 [0105-0109] on (support by) the first side (top of 1) of the silicon carbide substrate (10 and 1 of substrate 100) fig. 7 [0106].
Regarding claim 17, Ishibashi teaches a semiconductor body (300) fig. 7 [0105] comprising:
a silicon carbide substrate (10 and 1 of substrate 100) fig. 7 [0106] (1, 10 formed of silicon carbide) [0112];
an epitaxial silicon carbide layer system (121-123 of 120) fig. 7 [0105-0109] on a first side of the silicon carbide substrate on (supported by) a first side (top of 1) of the silicon carbide substrate (10 and 1); and
an interruption layer (11) fig. 7 [0105-0106];
wherein the interruption layer (11) is at least one of:
embedded (vertically embedded) into the silicon carbide substrate (10 and 1) at a vertical distance (non-zero thickness of 1) from the first side (top of 1) of the silicon carbide substrate (10 and 1 of 100) fig. 7 [0105].
Regarding claim 18, Ishibashi teaches the semiconductor body (300) fig. 7 [0105] of claim 17. Ishibashi also teaches wherein the interruption layer (11) fig. 7 [0106] is at least one of an amorphous layer [0016, 0061] and/or a porous layer [0058] (connection layer 11 may be both amorphous [0016] and provided with substantial degree of porosity [0013]).
Regarding claim 19, Ishibashi teaches a method of manufacturing [see fig. 8, 0111] a semiconductor body (300) fig. 7 [0105], comprising:
providing [see fig. 8, 0112] a silicon carbide substrate (10 and 1 of substrate 100) fig. 7 [0106] (1, 10 formed of silicon carbide) [0112];
forming [see figs. 9-10, 0114-0115] an epitaxial silicon carbide layer system (121-123 of 120) fig. 7 [0105-0109] on (supported by) a first side (top of 1) of the silicon carbide substrate (10 and 1); and
forming [see fig. 9, 0112] an interruption layer (11) fig. 7 [0106];
wherein the interruption layer (11) is at least one of:
(vertically) embedded into the silicon carbide substrate (between 10 and 1 portions of 100).
Regarding claim 20, Ishibashi teaches the method [see fig. 8, 0111] of claim 19. Ishibashi also teaches wherein the interruption layer (11) fig. 7 [0106] is at least one of:
embedded (vertically embedded) into the silicon carbide substrate (10 and 1) at a vertical distance (non-zero thickness of 1) from the first side (top of 1) of the silicon carbide substrate (10 and 1 of 100) fig. 7 [0105].
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pu (CN Pub No CN107579115A). (see attached translation for [line] citations)
Regarding claim 1, Pu teaches a semiconductor die [see fig. 1, lines 192-199] (comprising block of semiconductor material 1 [line 200]) comprising:
a semiconductor device (comprising 10) fig. 1 [lines 223-228] (component of semiconductor device of fig. 1) in a semiconductor body (comprising 1-6) fig. 1 [lines 200-218] (doped SiC [lines 200-218] semiconductor [lines 51-54]),
the semiconductor body (1-6) comprising:
a silicon carbide substrate (1) fig. 1 [lines 200-202];
an epitaxial silicon carbide layer system (comprising 2 and 4-7) fig. 1 [lines 202-222] (each formed by epitaxial growth) on (supported by) a first (top) side of the silicon carbide substrate (1); and
an interruption layer (3) fig. 1 [lines 205-207];
wherein the interruption layer (3) is at least one of:
embedded into the epitaxial silicon carbide layer system (comprising 2 and 4-7) at a/the vertical distance (thickness of layer 2) [lines 203-204] from the first (top) side of the silicon carbide substrate (1).
Regarding claim 2, Pu teaches the semiconductor die [see fig. 1, lines 192-200] of claim 1. Pu also teaches wherein the vertical distance (thickness of layer 2) [lines 203-204] between the first (top) side of the silicon carbide substrate (1) fig. 1 [lines 200-202] and the interruption layer (3) fig. 1 [lines 205-207] is at least 0.1 µm and not more than 1 µm (thickness of layer 2 is 0.1 µm to 3 µm [lines 203-204], encompassing the claimed range).
Regarding claim 3, Pu teaches the semiconductor die [see fig. 1, lines 192-200] of claim 1. Pu also teaches wherein the interruption layer (3) fig. 1 [lines 205-207] has a vertical thickness of at least 0.1 µm and not more than 5 µm (thickness of layer 3 is 0.1 µm to 3 µm [lines 206-207], overlapping the claimed range with a narrower range).
Regarding claim 4, Pu teaches the semiconductor die [see fig. 1, lines 192-200] of claim 1. Pu also teaches wherein the interruption layer (3) fig. 1 [lines 205-207] is a highly doped layer (is considered to be highly-doped p+ layer, ‘highly’ being a relative term).
Regarding claim 6, Pu teaches the semiconductor die [see fig. 1, lines 192-200] of claim 1. Pu also teaches wherein the epitaxial silicon carbide layer system (comprising 2 and 4-7) fig. 1 [lines 202-222] (each formed by epitaxial growth) comprises a device layer comprising 5-7) fig. 1 [lines 202-218] (hosting device components like 9 [lines 231-233]) and a buffer layer (comprising 2 and 4) fig. 1 [lines 202-218] (acting as a buffer between 1 and 5), the buffer layer (comprising 2 and 4) being arranged between the device layer (comprising 5-7) and the silicon carbide substrate (1) and being doped with a higher doping concentration (in layer 2 portion) [lines 256-257] than the device layer (in layer 6 portion) [lines 264-265] (2 of buffer layer may have minimum dopant concentration 5x10^17 atoms/cm^3 [lines 256-257], which is higher than a maximum dopant concentration of 6 of device layer, which may be 1x10^17 atoms/cm^3 [lines 264-266]).
Regarding claim 7, Pu teaches the semiconductor die [see fig. 1, lines 192-200] of claim 6. Pu also teaches wherein the interruption layer (3) fig. 1 [lines 205-207] is (vertically) embedded into (between portions of) the buffer layer (comprising 2 and 4) fig. 1 [lines 202-218], a lower portion (2) of the buffer layer (2 and 4) arranged between the interruption layer (3) and the silicon carbide substrate (1) fig. 7 [lines 200-202] and an upper portion (4) of the buffer layer (2 and 4) arranged between the device layer (5-7) and the interruption layer (3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (U.S. PG Pub No US2013/0092956A1), as applied in claim 1 above, in view of Paek (U.S. PG Pub No US2021/0175182A1).
Regarding claim 12, Ishibashi teaches a package (300) [0105] (packaged components) comprising:
the semiconductor die (300) fig. 7 [0105] of claim 1.
However, Ishibashi does not explicitly disclose and
a casing,
wherein the semiconductor die (300) is mounted and electrically contacted in the casing.
Paek teaches a package (100) fig. 1 [0015] comprising:
a casing (140 with 160 encasing 105) fig. 1 [0015-0016],
wherein the semiconductor die (105) fig. 1 [0015] is mounted on and electrically contacted (through 110, 115 connection(s) [0015]) in the casing (140 with 160).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have packaged the semiconductor die of Ishibashi in the package casing of Paek [0015-0016] in order to protect the semiconductor die [0016] and mechanically support wires for extra electrical connections formed with the die [0016], as taught by Paek.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi (U.S. PG Pub No US2013/0092956A1), as applied in claim 13 above, in view of Muri (U.S. PG Pub No US2019/0074212A1).
Regarding claim 16, Ishibashi teaches the method [see fig. 8, 0111] of claim 13. However, Ishibashi does not explicitly disclose wherein the interruption layer (11) fig. 7 [0105-0106] is made by a high dose implantation between a deposition of the lower portion of a buffer layer and a deposition of the upper portion of the buffer layer.
Muri teaches a method [see figs. 9A-9C, 0114] wherein the interruption layer (780) fig. 9C [0120-0121] is made by a high dose implantation [0121] between (vertically between) a deposition (placement) of the lower portion of a buffer layer (750) fig. 9A [0116] and a deposition of the upper portion (represented by 159) fig. 9A [0116] of the buffer layer (comprising 159 and 750).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have packaged the semiconductor die of Ishibashi such that the interruption layer is implanted with a relatively high dose of dopants [0121] in order to facilitate low resistive connections between it and adjacent structures [0121], as taught by Muri.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they all feature semiconductor devices with silicon carbide substrates, epitaxial layer structures, and interrupting layers therebetween.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 07/23/2026
Prosecution Insights