Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Power transistor with a temperature sensing element.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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1. Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,074,158 in view of Ahlers et al. Publication No. US 2016/0072376. Although the claims at issue are not identical, they are not patentably distinct from each other. The patented claims disclose almost all of the claim limitations of the instant application as shown below:
US Patent 12,074,158
Instant Application
1. A semiconductor device comprising:
1. A semiconductor device comprising:
A semiconductor chip;
a semiconductor chip;
a power transistor formed in the semiconductor chip; and
a power transistor formed in the semiconductor chip, the power transistor being a trench gate type;
a temperature sensing element configured to detect heat generation in the power transistor, wherein
a temperature sensing element configured to detect heat generation in the power transistor, wherein
the semiconductor chip includes:
the semiconductor chip includes:
a first electrode formed on a first-principle-face side of the semiconductor chip; and
a first electrode formed on a first-principle-face side of the semiconductor chip; and
a plurality of pads formed on the first-principle-face side of the semiconductor chip so as to be arranged in a lopsided manner, and
a plurality of pads formed on the first-principle-face side of the semiconductor chip so as to be arranged in a lopsided manner, and
the temperature sensing element is disposed in a vicinity of the power transistor.
the temperature sensing element is disposed in a vicinity of the power transistor.
2. The semiconductor device according to claim 1, wherein a second electrode is formed as a substrate electrode for applying a supply voltage to the semiconductor chip.
2. The semiconductor device according to claim 1, wherein a second electrode is formed as a substrate electrode for applying a supply voltage to the semiconductor chip.
3. The semiconductor device according to claim 2, further comprising: a power line formed on the first-principle-face side of the semiconductor chip; and a via connecting between the substrate electrode and the power line.
3. The semiconductor device according to claim 2, further comprising: a power line formed on the first-principle-face side of the semiconductor chip; and a via connecting between the substrate electrode and the power line.
4. The semiconductor device according to claim 3, wherein the power transistor is configured to function as a high-side switch of which the first electrode is connected to a load and of which the second electrode is connected to a power terminal.
4. The semiconductor device according to claim 3, wherein the power transistor is configured to function as a high-side switch of which the first electrode is connected to a load and of which the second electrode is connected to a power terminal.
5. The semiconductor device according to claim 2, wherein the power transistor is configured to function as a low-side switch of which the first electrode is connected to a ground terminal and of which the second electrode is connected to a load.
5. The semiconductor device according to claim 2, wherein the power transistor is configured to function as a low-side switch of which the first electrode is connected to a ground terminal and of which the second electrode is connected to a load.
6. The semiconductor device according to claim 1, wherein the first electrode has formed therein a slit through which a conductor from the temperature sensing element is led up to an edge of the first electrode.
6. The semiconductor device according to claim 1, wherein the first electrode has formed therein a slit through which a conductor from the temperature sensing element is led up to an edge of the first electrode.
7. The semiconductor device according to claim 6, wherein the slit is formed to extend in a direction opposite to one pad among the plurality of pads.
7. The semiconductor device according to claim 6, wherein the slit is formed to extend in a direction opposite to one pad among the plurality of pads.
8. The semiconductor device according to claim 7, wherein the plurality of pads are arranged in a lopsided manner on the first electrode such that current concentrates most at a corner of the one pad, that is closest to a temperature protection circuit.
8. The semiconductor device according to claim 7, wherein the plurality of pads are arranged in a lopsided manner on the first electrode such that current concentrates most at a corner of the one pad, that is closest to a temperature protection circuit.
9. The semiconductor device according to claim 8, wherein the temperature sensing element is disposed in a vicinity of the corner.
9. The semiconductor device according to claim 8, wherein the temperature sensing element is disposed in a vicinity of the corner.
10. The semiconductor device according to claim 8, wherein the temperature sensing element is arranged along, of a plurality of directions pointing from the corner to edges of the first electrode, a direction along which a distance from the corner to an edge is longer.
10. The semiconductor device according to claim 8, wherein the temperature sensing element is arranged along, of a plurality of directions pointing from the corner to edges of the first electrode, a direction along which a distance from the corner to an edge is longer.
11. The semiconductor device according to claim 8, wherein the plurality of pads comprises a main pad and a sub pad, the sub pad being smaller than the main pad.
11. The semiconductor device according to claim 8, wherein the plurality of pads comprises a main pad and a sub pad, the sub pad being smaller than the main pad.
12. The semiconductor device according to claim 7, wherein the temperature sensing element is arranged near the center of one side of the one pad.
15. The semiconductor device according to claim 7, wherein the temperature sensing element is arranged near the center of one side of the one pad.
13. The semiconductor device according to claim 1, further comprising: a temperature protection circuit configured to forcibly turn OFF the power transistor when the temperature sensing element detects abnormal heat generation in the power transistor.
12. The semiconductor device according to claim 1, further comprising: a temperature protection circuit configured to forcibly turn OFF the power transistor when the temperature sensing element detects abnormal heat generation in the power transistor.
14. An electronic appliance comprising: the semiconductor device according to claim 13.
13. An electronic appliance comprising: the semiconductor device according to claim 13.
15. A vehicle comprising: a battery; and the electronic appliance according to claim 14, the electronic appliance operating by being fed with a supply voltage from the battery.
14. A vehicle comprising: a battery; and the electronic appliance according to claim 14, the electronic appliance operating by being fed with a supply voltage from the battery.
The patented claim 1 does not disclose that the power transistor is a trench type.
Ahlers discloses a semiconductor chip [Fig. 1, 103], a power transistor [Fig. 1, 101], a temperature sensing element [par. 0040, detecting a temperature value] to detect heat generation in the power transistor [abstract]; wherein the power transistor comprises at least one gate trench comprising an insulation and a gate electrode [page 14, claim 4, lines 1-3]. It would have been obvious to one of ordinary kill in the art before the effective filing date of the claimed invention to incorporate Ahler’s trench type transistor, for the benefit of preventing the power transistor from entering runaway where increasing temperature leads to uncontrolled increases in current and eventual failure.
Allowable Subject Matter
Claims 1-15 are allowed, pending the filing of the terminal disclaimer as indicated above.
The prior art by Kinouchi et al. discloses a semiconductor device comprising:
a power transistor [Fig. 4, MOSFET 101; par. 0127] formed in the semiconductor silicon substrate [Fig. 4, 121], a temperature sensing element [Fig. 4, first sense cell group 103 and a second sense cell group 104; par. 0131, 0132] configured to detect heat generation in the power transistor, wherein the semiconductor substrate includes: a first electrode [Fig. 4, source electrode 106] formed on a first-principle-face side.
However, Kinouchi does not disclose a plurality of pads formed on the first-principle-face side of the semiconductor chip so as to be arranged in a lopsided manner. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2838
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