DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US Pub. 2022/0020404).
Regarding claim 1, Fig. 5 of Cho discloses a semiconductor memory comprising:
a memory block [100] including a plurality of pages [NS0 to NSn]; and
a read/write circuit [210] including a plurality of page buffers [PBU0 to PBUn] connected to bit lines [BL0 to BLn] of the memory block,
wherein the plurality of page buffers [PBU0 to PBUn] is capable of storing previous program data of a page programmed in a just previous program operation or specific data, and adjusting an evaluation period in a program verify operation of a currently selected page, based on the previous program data or the specific data [since page buffer circuit 200 of Cho is similar to page buffer circuit 160 of applicant, circuit 200 of Cho is capable of perform storing previous program data and adjusting an evaluation period].
Regarding claim 2, Fig. 6 of Cho discloses wherein each of the plurality of page buffers includes: a bit line controller [HVU and NM5] connected between any one of the bit lines [BL] and a sensing node [SO], the bit line controller capable of adjusting a potential level of the sensing node [SO, by turning on or off transistors HVU and NM5], based on a cell current amount of the bit line [BL], by performing an evaluation operation; a first latch unit [SL] connected to the sensing node [SO], the first latch unit capable of storing the previous program data or the specific data; and a second latch unit [FL] configured to latch verify data, based on the potential level of the sensing node.
Regarding claim 3, Fig. 6 of Cho discloses wherein the first latch unit [SL] is capable of [capable of has been held that the recitation that an element is “capable of” performing a function is not a positive limitations but only requires the ability to so perform. It does not constritue a limitations in any patentable sense. In re Hutchison, 69 USPQ 138] adjusting the evaluation period by applying a power voltage to the sensing node or interrupting the application of the power voltage to the sensing node in the evaluation operation.
Regarding claim 4, Fig. 6 of Cho discloses wherein the first latch unit includes: a latch connected between a first node [SO] and a second node [a node that directly connects to PRECHARGE CIRCUIT], the latch capable of latching the previous program data or the specific data; and a first transistor [HVU] and a second transistor [NM5], connected in series between a power voltage [power on BL] and the sensing node [SO], and wherein the first transistor [HVU] is capable of being turned on or turned off in response to a transmission signal [BLSLT], and the second transistor [NM5] is capable of being turned on or turned off in response to a potential of the first node [SO].
Regarding claim 5, Fig. 6 of Cho discloses wherein the first latch unit is capable of [capable of has been held that the recitation that an element is “capable of” performing a function is not a positive limitations but only requires the ability to so perform. It does not constritue a limitations in any patentable sense. In re Hutchison, 69 USPQ 138] setting an operation period of the evaluation operation as a second evaluation period shorter than a first evaluation period by applying the power voltage to the sensing node in the evaluation operation, when the first node is controlled to have a logic low level as the previous program data or the specific data is latched by the latch.
Allowable Subject Matter
Claims 6-8 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 6-8, the prior art does not teach or suggest either alone or in combination a method for operating a semiconductor memory, the method comprising: performing an evaluation operation of adjusting a potential level of a sensing node of the page buffer, based on a current amount of the bit lines, and then performing a program verify operation of latching verify data corresponding to the potential level of the sensing node, wherein the evaluation operation is performed during an evaluation period set as a first evaluation period or a second evaluation period shorter than the first evaluation period, based on the previous program data or the specific data, which is stored in the first latch unit and in combination with other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825