Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I in the reply filed on August 24, 2026 is acknowledged. The traversal is on the ground(s) that "the identified groups relate to a common generic concept, are not mutually exclusive, and would not impose an undue burden on the Examiner to search and examine the claims corresponding to both identified groups". This is not found persuasive because while Invention II generally relates to all limitations of Invention I, Invention I could be made by a materially different process, chiefly through a different sequence of steps in the process. In addition, while Invention II contains many similar limitations to Invention II, the fact that it is a method of manufacture requires a completely different search from Invention I, and so would impose an undue burden on the Examiner for searching.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emerson (US 20200035550 A1), in view of Lin (US 20200273812 A1), Luekenbach (US 20170321966 A1), and Choong (US 20180226322 A1).
Regarding independent claim 1, Emerson teaches an electronic package, comprising: a wiring structure (Fig. 10, 216; [0033], "The ILD layers 216 include conductive routing structures to form interconnections through associated PMD layer contacts 214 to interconnect various electronic components of the wafer 200 to one another, and to provide external connectivity to various ones of the electronic component features."); and a thermoelectric circuit structure disposed on the wiring structure (Fig. 10, 220; [0048], "In this example, the processed wafer 200 includes a thermally conductive material 1000 deposited over a thermal circuit component of the metallization structure (e.g., shown as a conductive routing structure 220).").
However, Emerson does not teach electronic components disposed on and electrically connected to the wiring structure; and a thermal conductive structure erected on the wiring structure and covering the electronic components, wherein the thermal conductive structure includes a thermal conductive board and thermal conductive pillars, and the thermal conductive board and the thermal conductive pillars form interconnected hollow chambers for injecting a working fluid thereinto, wherein one end of each of the thermal conductive pillars is connected to the thermal conductive board, and the other end is connected to the thermoelectric circuit structure to generate a voltage via a temperature difference to drive the working fluid to flow.
However, in the same field of endeavor, Lin teaches electronic components disposed on and electrically connected to the wiring structure ([0008], "The electronic component is disposed on the substrates or the redistribution layer."); and a thermal conductive structure erected on the wiring structure and covering the electronic components (Fig. 9A, 908, 902; [0107], "The substrate 902 has a wiring structure therein."), wherein the thermal conductive structure includes a thermal conductive board and thermal conductive pillars (Fig. 9A, 908; [0116], "As shown in FIG. 9A, the sidewalls of the heat spreader 908 may be disposed over the frame 113. In particular, the heat spreader 908 has an upper portion on the thermal interface material 906, and a lower portion on the edge of the upper portion."), and wherein one end of each of the thermal conductive pillars is connected to the thermal conductive board (Fig. 9A, 908, (It is clear they are connected - in fact, they are one piece)), Lueckenbach teaches and the thermal conductive board and the thermal conductive pillars form interconnected hollow chambers for injecting a working fluid thereinto (Fig. 3, 102; [0028], "In some forms, the energy dissipater 102 may be a vapor chamber or heat pipe forming a hollow chamber therein which contains a working fluid."), and Choong teaches and the other end is connected to the thermoelectric circuit structure to generate a voltage via a temperature difference to drive the working fluid to flow (Fig. 3C, 305, 306, 301, 302; [0017], "A thermoelectric circuit including a plurality of thermal bond pads 305 and substrate bond pads 306 alternately connected in series with p-type thermoelectric bond wires 301 and n-type thermoelectric bond wires 302 and a voltage source 308 allow for the thermoelectric bond wires 301, 302 to thermoelectrically transfer thermal energy between the thermal bond pads 305 and the substrate bond pads 306.", [0022], "At 603, a voltage source can be applied to a thermoelectric circuit associated with the package. The thermoelectric circuit can share a ground reference but is otherwise electrically isolated from the integrated circuits of the stack of the integrated circuit dies. At 604, in response to the applied voltage source, thermal energy from the one or more stacked integrated circuits dies can be thermoelectrically transferred from a thermal bond pad attached to one of the one or more stacked integrated circuits dies to a heat sink, such as a substrate bond pad or a cooling bond pad located on the package.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic package of Emerson with the electronic components and thermal conductive structure of Lin so that "heat-dissipation efficiency of the semiconductor package structure can be improved", (Lin, [0037]), the hollow chambers with working fluid of Lueckenbach so as "to passively dissipate heat", (Lueckenbach, [0028]), and the thermoelectric circuit structure of Choong so that "thermal energy can be thermoelectrically transferred to a heat sink, such as a substrate bond pad or a cooling bond pad located on the package", (Choong, [0022]).
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emerson (US 20200035550 A1), in view of Lin (US 20200273812 A1), Luekenbach (US 20170321966 A1), Choong (US 20180226322 A1), and Lee (US 20220367416 A1).
Regarding dependent claim 2, Emerson, as previously modified by Lin, Lueckenbach, and Choong, teaches the electronic package of claim 1. However, as previously combined, they do not tach wherein the electronic components include a first electronic component, second electronic components, and a third electronic component, wherein the first electronic component has a first active surface and is disposed in a first encapsulation layer, each of the second electronic components has a second active surface and is disposed in a second encapsulation layer above the first encapsulation layer, the third electronic component has a third active surface and is disposed in a third encapsulation layer above the second encapsulation layer, and the third active surface is opposite to and electrically connected to the first active surface and the second active surface, respectively.
However, in the same field of endeavor, Lee teaches wherein the electronic components include a first electronic component, second electronic components, and a third electronic component, wherein the first electronic component has a first active surface and is disposed in a first encapsulation layer (Fig. 11, 20, 50S; [0142], "In some embodiments, the auxiliary encapsulation portion 50S may cover the first auxiliary chip 20a...",), each of the second electronic components has a second active surface and is disposed in a second encapsulation layer above the first encapsulation layer (Fig. 12, 10, 52; [0156], "The lower semiconductor chip 10 may include a lower semiconductor substrate 12 having an active surface…", [0129], "The first encapsulant 52 may encapsulate the semiconductor chip 10…"), the third electronic component has a third active surface and is disposed in a third encapsulation layer above the second encapsulation layer (Fig. 14, 410, 450; [0153], "The upper semiconductor chip 410 may include an upper semiconductor substrate 412 having an active surface…", [0165], "In some embodiments, the upper molding member 450 may cover the upper surface of the third package substrate 300 and surround the upper semiconductor chip 410 and the upper underfill layer 460."), and the third active surface is opposite to and electrically connected to the first active surface and the second active surface, respectively (Fig. 14, 410, 10, 20, (The active surface is on the other side of the package from the two other chips and can be seen to be electrically connected to them through vias and bumps)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Emerson, Lin, Lueckenbach, and Choong with the electronic components of Lee so as to function as "passive devices and active devices which are attached to the package substrate", (Lee, [0003]).
Regarding dependent claim 3, Emerson, as previously modified by Lin, Lueckenback, Choong, and Lee, teaches the electronic package of claim 2. However, as previously combined, they do not teach wherein the first active surface has a plurality of first connection pads, thereon, and at least a portion of the plurality of first connection pads are directly electrically connected to the third active surface.
However, Lee further teaches wherein the first active surface has a plurality of first connection pads thereon (Fig. 14, 20, 28; [0044], "The auxiliary chip 20 may be connected to some of the plurality of substrate lower surface pads 124 of the package substrate 100 through a plurality of chip terminals 28."), and at least a portion of the plurality of first connection pads are directly electrically connected to the third active surface (Fig. 14, 410, 10, 20, (The active surface is on the other side of the package from the two other chips and can be seen to be electrically connected to them through vias and bumps)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Emerson, Lin, Lueckenbach, Choong, and Lee with the connection pads of Lee so that "the plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate", (Lee, [0038]).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emerson (US 20200035550 A1), in view of Lin (US 20200273812 A1), Luekenbach (US 20170321966 A1), Choong (US 20180226322 A1), Lee (US 20220367416 A1), and Ng (US 20200402965 A1).
Regarding dependent claim 4, Emerson, as previously modified by Lin, Lueckenback, Choong, and Lee, teaches the electronic package of claim 2. However, as previously combined, they do not teach further comprising a circuit structure, wherein the circuit structure is disposed between the second electronic components and the third electronic component, and the circuit structure has a first surface, a second surface opposing the first surface, and a circuit layer, wherein the third active surface of the third electronic component is electrically connected to the second active surface of each of the second electronic components via the circuit layer.
However, in the same field of endeavor, Ng teaches further comprising a circuit structure (Fig. 2F, 20; [0036], "As shown in FIG. 2D, a circuit structure 20 is disposed on the first surface 25a of the encapsulation layer 25 and electrically connected to the conductive pillars 23 and the conductive bodies 22."), wherein the circuit structure is disposed between the second electronic components and the third electronic component (Fig. 2F, 20, 21, 26; [0054], "As compared with the prior art, the electronic package 2 according to the present disclosure disposes the first electronic component 21 and the second electronic component 26 on two sides of the circuit structure 20, respectively, and has various functions and high performance."), and the circuit structure has a first surface (Fig. 2D, 25a), a second surface opposing the first surface (Fig. 2D, 200), and a circuit layer (Fig. 2D, 201; [0037], "In an embodiment, the circuit structure 20 comprises a plurality of insulation layers 200 and a plurality of redistribution layers (RDLs) 201 formed on the insulation layers 200…"), wherein the third active surface of the third electronic component is electrically connected to the second active surface of each of the second electronic components via the circuit layer (Fig.2B, 21a, Fig. 2F, 20, 21, 26; [0031], "In an embodiment, the first electronic component 21 is a semiconductor chip and has an active surface 21a and an inactive surface 21b opposing the active surface 21a.", [0041], "In an embodiment, the second electronic component 26 is electrically connected to the conductive pad 202 via a plurality of conductive bumps 27...", [0036], "As shown in FIG. 2D, a circuit structure 20 is disposed on the first surface 25a of the encapsulation layer 25 and electrically connected to the conductive pillars 23 and the conductive bodies 22.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Emerson, Lin, Lueckenbach, Choong, and Lee with the circuit structure of Ng so as to "allow the package to be small and have more external contacts", (Ng, [0072]).
Regarding dependent claim 5, Emerson, as previously modified by Lin, Lueckenback, Choong, Lee, and Ng, teaches the electronic package of claim 4. Ng further teaches wherein the third electronic component is disposed on the second surface of the surface structure via the third active surface (Fig. 2F, 26, 20; [0060], "The second electronic component 26 is disposed on the circuit structure 20 and electrically connected to the circuit structure 20.").
Regarding dependent claim 6, Emerson, as previously modified by Lin, Lueckenback, Choong, Lee, and Ng, teaches the electronic package of claim 4. Ng further teaches wherein each of the second electronic components is connected to the first surface of the circuit structure via the second active surface (Fig. 2D, 21, 22, 20; [0063], "In an embodiment, the first electronic component 21 has an active surface 21a bonded and electrically connected to the conductive bodies 22…", [0036], "As shown in FIG. 2D, a circuit structure 20 is disposed on the first surface 25a of the encapsulation layer 25 and electrically connected to the conductive pillars 23 and the conductive bodies 22.").
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Emerson (US 20200035550 A1), in view of Lin (US 20200273812 A1), Luekenbach (US 20170321966 A1), Choong (US 20180226322 A1), Lee (US 20220367416 A1), and Lin (US 20170033079 A1, hereinafter Lin2).
Regarding dependent claim 7, Emerson, as previously modified by Lin, Lueckenback, Choong, and Lee, teaches the electronic package of claim 2. However, as previously combined, they do not teach wherein the third electronic component is a graphics processor or a central processing unit, each of the second electronic components is a memory chip or a memory module, and the first electronic component is an auxiliary electronic component.
However, in the same field of endeavor, Lin2 teaches wherein the third electronic component is a graphics processor or a central processing unit (Fig. 1F, 300; [0046], "For example, the third electronic component 300 may be a memory die, a logic die including a CPU, a GPU, or a DRAM controller, or another suitable active electronic component."), and Lee further teaches each of the second electronic components is a memory chip or a memory module (Fig. 14, 10; [0039], "In some embodiments, the semiconductor chip 10 may be, for example, a memory semiconductor chip."), and the first electronic component is an auxiliary electronic component (Fig. 14, 20; [0040], "The auxiliary chip 20 may be a semiconductor chip of a different type from that of the semiconductor chip 10. ").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Emerson, Lin, Lueckenbach, Choong, and Lee with the graphics processor or CPU of Lin2 so as to be a "suitable active electronic component", (Lin2, [0046]), and with the memory chip and auxiliary chip of Lee "for assisting the operation of the main semiconductor chip" in computation, (Lee, [0040]).
Regarding dependent claim 8, Emerson, as previously modified by Lin, Lueckenback, Choong, and Lee, teaches the electronic package of claim 2. However, as previously combined, they do not teach further comprising a wiring structure disposed under the first electronic component, wherein the wiring structure is electrically connected to the first electronic component.
However, in the same field of endeavor, Lin2 teaches further comprising a wiring structure disposed under the first electronic component, wherein the wiring structure is electrically connected to the first electronic component (Fig. 1A, 160, 130, 140; [0017], "In some embodiments, the substrate 100 includes an insulating material layer 110, solder resist layers (solder mask layers) 120, conductive layers 130, and vias 140.", [0021], "Subsequently, one or more first electronic components 160 are bonded on the substrate 100.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the electronic device as described by the combination of Emerson, Lin, Lueckenbach, Choong, and Lee with the wiring structure of Lin2 so that the package can "be small in size, support multi-pin connection, operate at high speeds, and provide high functionality", (Lin2, [0005]).
Regarding dependent claim 9, Emerson, as previously modified by Lin, Lueckenback, Choong, Lee, and Lin2, teaches the electronic package of claim 8. Lin2 further teaches wherein the first electronic component is adhered onto the wiring structure via a die attach film (Fig. 1A, 170; [0021], "For example, the first electronic components 160 are attached to the dielectric layer 150 through an adhesive layer 170.").
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230111192 A1,.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 5712707996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights