Office Action Predictor
Last updated: April 17, 2026
Application No. 18/768,747

PRESERVING BLOCKS EXPERIENCING PROGRAM FAILURE IN MEMORY DEVICES

Non-Final OA §102§103
Filed
Jul 10, 2024
Examiner
NGUYEN, VAN THU T
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
micron technology Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
89%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
785 granted / 950 resolved
+14.6% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
981
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 950 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending and examined. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 8, 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,455,048 to Berckmann et al. (hereafter Berckmann). Regarding independent claim 1, Berckmann teaches a method comprising: receiving, by a processing device, a write command to program data to a block of a memory device (FIG. 1: when host 106 send to memory controller 105 a write command and data to be written, see 4:9-11); identifying, using a zone write pointer, a wordline of the block that addresses a set of memory cells for writing the data (FIG. 7A: e.g. identifying a starting/ending word line for pointer 742 of fragment 1); determining whether the identified wordline matches an entry in a data structure (e.g. when a selected word line is identified as bad word line, it is not selected as starting/ending word line for data fragment pointer 742, see 13:31-37); and responsive to determining that the identified wordline matches the entry in the data structure, updating the zone write pointer to select a new wordline associated with the block (see 13:23-37). Regarding independent claim 8, Berckmann teaches a system comprising: a memory device (FIG. 1A: memory chip 102); and a processing device (FIG. 1: memory controller 105), operatively coupled with the memory device, to perform operations comprising: receiving a write command to program data to a block of a memory device (FIG. 1: when host 106 send to memory controller 105 a write command and data to be written, see 4:9-11); identifying, using a zone write pointer, a wordline of the block that addresses a set of memory cells for writing the data (FIG. 7A: e.g. identifying a starting/ending word line for pointer 742 of fragment 1); determining whether the identified wordline matches an entry in a data structure (e.g. when a selected word line is identified as bad word line, it is not selected as starting/ending word line for data fragment pointer 742, see 13:31-37); and responsive to determining that the identified wordline matches the entry in the data structure, updating the zone write pointer to select a new wordline associated with the block (see 13:23-37). Regarding independent claim 15, Berckmann teaches a non-transitory computer-readable medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising: receiving a write command to program data to a block of a memory device (FIG. 1: when host 106 send to memory controller 105 a write command and data to be written into memory chip 102, see 4:9-11); identifying, using a zone write pointer, a wordline of the block that addresses a set of memory cells for writing the data; determining whether the identified wordline matches an entry in a data structure; and responsive to determining that the identified wordline matches the entry in the data structure, updating the zone write pointer to select a new wordline associated with the block. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-7, 9-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Berckmann in view of US 9,570,177 to Choi (hereafter Choi). Regarding dependent claim 2, Berckmann further teaches responsive to determining that a program fault occurred during a write operation to program the data to the new wordline (FIG. 8B: step 858, see 15:51-59). Berckmann does not teach the remaining limitaitons. Choi teaches determining a number of wordlines referenced by the data structure that are associated with the block (FIG. 14: bad page count); and responsive to determining that the number of wordlines fails to satisfy a threshold criterion (FIG. 14: step 1420, see 19:60-65, when the count of bad word line(s) < a threshold, see 18:15-28), releasing a spare wordline to be available for write operations (FIG. 12: releasing WLi .. WLi+2 for steps 1430-1450 of FIG. 14, also see 18:15-28 and 19:1-11). Since Berckmann and Choi are all from the same field of endeavor, the purpose disclosed by Choi would have been recognized in the pertinent art of Berckmann. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to set the number of failed wordlines to a predetermined threshold as suggested by Choi before considering the block to be a bad block, in order to reduce early block retirement and improve data storage capacity. Regarding dependent claim 3, Choi teaches responsive to determining that the number of wordlines satisfies the threshold criterion, marking the block in a grown bad block (GBB) data structure (FIG. 14: step 1460, see 18:15-22). Regarding dependent claim 4, Berckmann teaches responsive to determining that the number of wordlines fails to satisfy the threshold criterion, listing the new wordline in the data structure (see 15:65-16:6). Regarding dependent claim 5, even though Choi teaches responsive to determining that the number of wordlines satisfies the threshold criterion, marking the block in a grown bad block (GBB) data structure (FIG. 14: step 1460, see 18:15-22) instead of removing all entries associated with the block from the data structure. It would have been obvious to a person having ordinary skill in the art to realize that when a block is GBB, data structure should be removed because it is no longer need for the GBB. Regarding dependent claim 6, Choi teaches maintaining a spare wordline data structure, wherein each entry in the spare wordline data structure is associated with an inactive wordline capable of replacing a defective wordline in the block (FIG. 12: e.g. WLi-WLi+2, normal pages not programmed with data are seen as spare wordline, see 19:1-11). Regarding dependent claim 7, Choi teaches responsive to determining that the identified wordline fails to match the entry in the data structure, programming the data to the wordline (i.e. when the wordline is between the starting and ending wordlines). Regarding dependent claims 9-14, 16-20, see rejections applied to claims 2-7 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. December 28, 2025 /VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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Prosecution Timeline

Jul 10, 2024
Application Filed
Dec 28, 2025
Non-Final Rejection — §102, §103
Mar 16, 2026
Applicant Interview (Telephonic)
Mar 16, 2026
Examiner Interview Summary
Mar 31, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

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MEMORY DEVICE INCLUDING INTERFACE CIRCUIT AND METHOD OF OPERATING THE SAME
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Patent 12573450
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2y 5m to grant Granted Mar 10, 2026
Patent 12573449
METHODS OF TESTING NONVOLATILE MEMORY DEVICES AND NONVOLATILE MEMORY DEVICES
2y 5m to grant Granted Mar 10, 2026
Patent 12567470
SYSTEM AND METHOD FOR DYNAMIC INTER-CELL INTERFERENCE COMPENSATION IN NON-VOLATILE MEMORY STORAGE DEVICES
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
89%
With Interview (+6.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 950 resolved cases by this examiner. Grant probability derived from career allow rate.

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