Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on 7/10/2024 have been accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted up to this point have been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
[0078] describes “an outer edge or side of the source electrode 124 of the second transistor 110” however the examiner believes feature 124 corresponds to the second transistor 120, not 110.
[0094] describes “second reflective member 282 may have a width that is greater than the first reflective member 282” however the examiner believes feature “first reflective member 282” corresponds to the first reflective member 281.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 20, the applicant recites “the first storage capacitor” and “the second storage capacitor” however these were not introduced in claim 18. Thus this claim contains terms that lack antecedence basis.
For the sake of compact prosecution, the examiner interprets this claim 20 as if it were dependent on claim 19.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 18 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ota (US # 20200327844).
Regarding Claim 18, Ota teaches a display device, comprising:
a plurality of sub-pixels (display panel 110 includes RGB sub pixels; [0138]), wherein each of the plurality of sub-pixels includes:
a light emitting diode (111) having a first anode electrode (71; [0127]), a second anode electrode (72), and a cathode electrode (60);
a first driving transistor (112-1; see Figs. 6-7) including a first electrode (114-1) connected to the first anode electrode; and
a second driving transistor (112-2) including a first electrode (114-2) connected to the second anode electrode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Ota (US # 20200327844) in view of Kim-877 (US 20250133877).
Regarding Claim 1, Ota (US # 20200327844) teaches a display device, comprising:
a substrate (circuit board of display panel 110; [0119, 132-134]; see Fig. 6-7);
a plurality of sub-pixels (display panel 110 includes pixels arranged in a matrix, Fig. 6-7; [0138]) disposed on the substrate, each of the plurality of sub-pixels including an emitting area (area vertically aligned with LED 111 active layers) and a non-emitting area (area NOT vertically aligned with active layers)
a first thin film transistor (112-1; [0121-122]) disposed on the substrate in the non-emitting area;
a second thin film transistor (112-2; [0121-122]) disposed on the substrate in the non-emitting area; and
a light emitting diode (111; especially see details in Figs. 1) disposed on the substrate in the emitting area, the light emitting diode including a first p-type electrode (71 connecting to p-type layer 22-1) and a second p-type electrode (72 connecting to layer 22-2),
wherein the first p-type electrode is electrically connected to the first thin film transistor (71-1 is connected to 112-1; see Figs. 5-6) and the second p-type electrode (72-1 is connected similarly to 112-2) is electrically connected to the second thin film transistor (see Fig. 6 especially).
Although Ota discloses much of the claimed invention, it does not explicitly teach the sub-pixels having a design where the non-emitting area (area NOT vertically aligned with active layers) surrounds the emitting area.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Kim is in the same or analogous field, and it teaches an emitting area (EA1; see Fig. 6) and a non-emitting area (corresponds approximately to region vertically aligned with feature PDL), wherein the non-emitting area covers pixel contact structures and a transistor (TR).
A person having ordinary skill in the art would have recognized that modifying the pixel design of Ota with the surrounding PDL suggested by Kim would be obvious. Specifically, the modification suggested by Kim would be to employ a sub-pixels having a design where the non-emitting area (area NOT vertically aligned with active layers) surrounds the emitting area. The rationale for this obvious modification is that a PDL confines emission of light to a defined aperture and leaves the peripheral region of the sub-pixel available for the contact structures. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of defined apertures are well known in the art (see MPEP 2144.01).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ota (US # 20200327844) in view of Kim-877 (US 20250133877) and further view of Park (US # 20220399313).
Regarding Claim 2, Ota teaches the display device of claim 1, wherein the light emitting diode further includes:
an n-type semiconductor layer (21; [0050])
a first active layer (31), a second active layer (32), and an n-type electrode (60) disposed on the n-type semiconductor layer;
a first p-type semiconductor layer (22-1) disposed on the first active layer; and
a second p-type semiconductor layer (22-) disposed on the second active layer.
Although Ota in view of Kim discloses much of the claimed invention, it does not explicitly teach the device comprising a buffer layer disposed on the substrate under the n-type semiconductor layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Park is in the same or analogous field, and it teaches a device (see Fig. 16 and corresponding text) comprising a buffer layer (1651) disposed on a substrate (1658) under an n-type semiconductor layer (1653).
A person having ordinary skill in the art would have recognized that modifying the LED stack of Ota in view of Kim with the buffer layer suggested by Park would be obvious. Specifically, the modification suggested by Park would be to employ a device comprising a buffer layer disposed on the substrate under the n-type semiconductor layer. The rationale for this obvious modification is that such a buffer layer provides protection during chip separation from a growth substrate ([0187]) and it may also provide greater crystal order effects for the active layers. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of buffer layer are well known in the art (see MPEP 2144.01).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ota (US # 20200327844) in view of Kim-877 (US # 20250133877) and further view of Park (US # 20220399313) and Kim-542 (US # 20220344542).
Regarding Claim 14, Ota teaches a display device, comprising:
a substrate (circuit board of display panel 110; [0119, 132-134]; see Fig. 6-7);
a plurality of sub-pixels (display panel 110 includes pixels arranged in a matrix, Fig. 6-7; [0138]) disposed on the substrate, each of the plurality of sub-pixels including an emitting area (area vertically aligned with LED 111 active layers) and a non-emitting area (area NOT vertically aligned with active layers)
a light emitting diode (111; especially see details in Figs. 1) disposed on the substrate in the emitting area, the light emitting diode including:
a first p-type electrode (71 connecting to p-type layer 22-1) disposed on a first side of the n-type semiconductor layer (left side of 21)
a second p-type electrode (72 connecting to layer 22-2) disposed on a second side of the n-type semiconductor layer (right side of 21)
an n-type electrode (60) disposed on a
wherein the first p-type electrode (71) and the n-type electrode (60) are spaced apart from each other (shown), and
the second p-type electrode (72) and the n-type electrode (60) are spaced apart from each other (shown).
a first thin film transistor (112-1; [0121-122]) disposed on the substrate in the non-emitting area;
a second thin film transistor (112-2; [0121-122]) disposed on the substrate in the non-emitting area; and
a light emitting diode (111; especially see details in Figs. 1) disposed on the substrate in the emitting area, the light emitting diode including a first p-type electrode (71 connecting to p-type layer 22-1) and a second p-type electrode (72 connecting to layer 22-2),
wherein the first p-type electrode is electrically connected to the first thin film transistor (71-1 is connected to 112-1; see Figs. 5-6) and the second p-type electrode (72-1 is connected similarly to 112-2) is electrically connected to the second thin film transistor (see Fig. 6 especially).
Although Ota discloses much of the claimed invention, it does not explicitly teach the sub-pixels having a design where the non-emitting area (area NOT vertically aligned with active layers) surrounds the emitting area; and the n-type electrode disposed on a center of a buffer layer between the first and second p-type electrodes.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
The motivations for modifying the Ota device with Kim-877 (the non-emitting arera) and Park (the buffer layer) were given in the rejections for claims 1 and 2. Those modifications are deemed obvious for the same reasons.
The relative position of the n-type electrode with regards to the first and second p-type electrodes requires additional citation to prior-art teachings: Kim-542 is in the same or analogous field, and it teaches a pixel design comprising an n-type electrode (412) disposed on a center between a first (413) and a second (411) p-type electrode (see [0064, 76]).
A person having ordinary skill in the art would have recognized that modifying the electrode positioning of Ota in view of Kim-377 and further view of Park with the central n-type electrode suggested by Kim-542 would be obvious. Specifically, the modification suggested by Kim-542 would be to employ a display device comprising the n-type electrode disposed on a center of a buffer layer between the first and second p-type electrodes. The rationale for this obvious modification is that centering the n-type electrode provides the same series resistance to both p-type electrodes, which allows better control of the separate pixel electrodes.
Claim 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ota (US # 20200327844) in view of Li (US # 20190035974).
Regarding Claim 19, Ota teaches the display device of claim 18, wherein the first driving transistor includes a gate electrode (gate of TFT 112-1) and a second electrode (S/D electrode of TFT),
the second driving transistor includes a gate electrode (gate of TFT 112-2) and a second electrode (S/D electrode of TFT),
Although Ota discloses much of the claimed invention, it does not explicitly teach the device wherein each of the plurality of sub-pixels includes a first storage capacitor connected between the gate electrode of the first driving transistor and the second electrode of the first driving transistor, and each of the plurality of sub-pixels includes a second storage capacitor connected between the gate electrode of the second driving transistor and the second electrode of the second driving transistor.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Li is in the same or analogous field, and it teaches a device (see Fig. 5 and corresponding text at [0047]) wherein each of a plurality of sub-pixels (1; shown in Fig. 1, and each light-emitting element is associated with a pixel drive circuit, shown in Fig. 5) includes a first storage capacitor (C) connected between a gate electrode of a first driving transistor (Td, shown with gate electrode) and a second electrode of the first driving transistor (the side with VDD).
A person having ordinary skill in the art would have recognized that modifying the driving transistor circuits of Ota with the capacitor suggested by Li would be obvious. Specifically, the modification suggested by Li would be to employ a device wherein each of the plurality of sub-pixels includes a first storage capacitor connected between the gate electrode of the first driving transistor and the second electrode of the first driving transistor, and each of the plurality of sub-pixels includes a second storage capacitor connected between the gate electrode of the second driving transistor and the second electrode of the second driving transistor. The rationale for this obvious modification is that a capacitor for each of the driving T circuits provides independent driving of the two light-emitting cells of Ota ([047] and see also [0075, 128] of Ota). This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of capacitors in LED circuits are well known in the art (see MPEP 2144.01).
Regarding Claim 20, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejection above, Li, as applied to claim 19, teaches the display device wherein each of the plurality of sub-pixels includes a first switching transistor (scanning transistor T) configured to supply a first data voltage from a first data line (41) to an electrode of the first storage capacitor (node O, which is connected to capacitor C), and each of the plurality of sub-pixels includes a second switching transistor (transistor T for the second driving circuit, explained in the rejection of claim 19) configured to supply a second data voltage from a second data line (42) to an electrode of the second storage capacitor (capacitor of the second driving circuit, explained in the rejection of claim 19).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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