DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed August 7, 2026, have been fully considered but they are not persuasive. Applicant argues that Jeon’s barrier layer would not be penetrated because doing so would defeat its purpose. However, Jeon expressly teaches that cavity C penetrates a portion of insulating layer 114 and that insulating layer 114 may serve as a barrier layer while being partially processed (Jeon [0074, 0076]). Applicant’s arguments regarding Lee and Choi are not persuasive because the rejection relies on Lee for the solder resist/cavity structure, Choi for the stepped cavity portions, and Jung for the via exposure relied upon in the combination. Arguments directed to the prior mapping are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20220141953 A1) and in further view of Lee et al. (US 9894764 B2) and Choi et al. (KR 20110104395 A) and Jung et al. (KR 102521788 B1)
Regarding Claim 1 – Jeon teaches a printed circuit board (Fig 7; PCB 100C), comprising: a first insulating layer (Fig 7; insulating layer 114); a first wiring layer that is buried in the first insulating layer (Fig 7; wiring layer 124; Jeon [0074, 0081]); a first via that is disposed within a first via hole in the first insulating layer (Fig 7; wiring via layer 134, insulating layer 114; Jeon [0083, 0087]); a second insulating layer that is disposed below the first insulating layer (Fig 7; insulating layer 113; Jeon [0079]); a second wiring layer that is buried in the second insulating layer (Fig 7; wiring layer 123; Jeon [0081]); and a cavity that extends along a height direction… and penetrating a portion of the first insulating layer (Fig 7; cavity C, insulating layer 114; Jeon [0074, 0088] teaches “cavity C penetrating through the fifth insulating layer 115 and a portion of the fourth insulating layer 114”).
Jeon does not explicitly disclose a first solder resist layer that is disposed on the first insulating layer; and a cavity that extends along a height direction by penetrating the first solder resist layer; wherein the cavity includes a first portion, a second portion, and a third portion having different widths, along the height direction, the first portion is disposed on the second portion and the third portion is disposed on the first portion, and the first via is exposed through the second portion of the cavity.
Lee teaches a first solder resist layer that is disposed on the first insulating layer (Fig 2; solder resist layer 270, insulating layer 220); and a cavity that extends along a height direction by penetrating the first solder resist layer (Fig 2; cavity 271, solder resist layer 270, insulating layer 220; Lee states “the solder resist layer 270 formed on one surface of the first insulating layer 220 includes a cavity 271 having a through-hole shape”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon with a first solder resist layer that is disposed on the first insulating layer; and a cavity that extends along a height direction by penetrating the first solder resist layer as taught by Lee to protect the circuit layer while exposing the needed contact region, Lee teaches the solder resist layer protects the circuit layer from soldering damage and oxidation.
Choi teaches the cavity includes a first portion (Figs 2D-2F; intermediate cavity portion above the second portion at 130), a second portion (Figs 2D-2F; lower narrower cavity portion near 121), and a third portion (Figs 2D-2F; upper wider cavity portion above the first portion at 210) having different widths, along the height direction, the first portion is disposed on the second portion and the third portion is disposed on the first portion (Figs 2D-2F; cavity circuit pattern 121, cavity insulating layer 130, second cavity insulating layer 210; Choi [0051, 0056-0057, 0060-0063] teaches “a stepped portion of a cavity is formed and a void space becomes larger as it goes upward” and “the lower width is narrower than the upper width”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon in view of Lee with the cavity includes a first portion, a second portion, and a third portion having different widths, along the height direction, the first portion is disposed on the second portion and the third portion is disposed on the first portion as taught by Choi to improve cavity depth control and avoid “damaging the internal circuit of the cavity in the process of plating, image, etching, etc.”.
Jung teaches the first via is exposed through the second portion of the cavity (Figs 1-2; cavity C; Jung [0049, 0114]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon in view of Lee and Choi with the first via is exposed through the second portion of the cavity as taught by Jung in order to allow a semiconductor chip to be mounted in the cavity through an exposed conductive connection, Jung [0067-0068] teaches “The metal bump 230 is stacked on the through electrode 114 exposed by the cavity C” and that “The semiconductor chip 200 is embedded and mounted in the cavity C… via the metal bump 230”.
Regarding Claim 4 – Jeon in view of Lee, Choi, and Jung teaches the printed circuit board of claim 1, wherein a first width of the first portion, a second width of the second portion, and a third width of the third portion are different from each other (Choi; Figs 2D-2F; 121, 130, 210; Choi [0051, 0056-0057, 0063] states “the second cavity insulating layer has a shorter length than the first cavity insulating layer” and “a cavity having a structure in which a stepped portion of a cavity is formed and a void space becomes larger as it goes upward can be formed” and “the lower width is narrower than the upper width”).
Regarding Claim 5 – Jeon in view of Lee, Choi, and Jung teaches the printed circuit board of claim 4, wherein the second width of the second portion is less than each of the first width of the first portion and the third width of the third portion (Choi; Figs 2D-2F; 121, 130, 210; Choi [0056, 0063] states “a void space becomes larger as it goes upward can be formed” and “the lower width is narrower than the upper width”).
Regarding Claim 8 – Jeon in view of Lee, Choi, and Jung teaches the printed circuit board of claim 1, further comprising: a second via disposed within a second via hole in the second insulating layer (Jeon; Fig 7; wiring via layer 133, insulating layer 113; Jeon [0083, 0087]); a third insulating layer disposed below the second insulating layer (Jeon; Fig 7; insulating layer 112; Jeon [0079]); and a third via disposed within a third via hole in the third insulating layer (Jeon; Fig 7; wiring via layer 132, insulating layer 112; Jeon [0083, 0087]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20220141953 A1) in view of Lee et al. (US 9894764 B2) and Choi et al. (KR 20110104395 A) and Jung et al. (KR 102521788 B1) and in further view of Ko et al. (KR 20220136869 A)
Regarding Claim 2 – Jeon in view of Lee, Choi, and Jung teaches the printed circuit board of claim 1, but does not explicitly disclose wherein the second portion of the cavity is plural in number, and a surface of the first insulating layer between the plurality of second portions included in the cavity has a plurality of protrusions protruding toward the first portion.
Ko teaches the second portion of the cavity is plural in number, and a surface of the first insulating layer between the plurality of second portions included in the cavity has a plurality of protrusions protruding toward the first portion (Figs 3-6; first insulating layer 111, first cavity C1, second cavity C2, protrusions P; Ko [0049, 0054, 0083]).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon in view of Lee, Choi, and Jung with the second portion of the cavity is plural in number, and a surface of the first insulating layer between the plurality of second portions included in the cavity has a plurality of protrusions protruding toward the first portion as taught by Ko because Ko [0041] states “the first cavity C1 and the plurality of protrusions P… facilitate bonding between the electronic component and the printed circuit board 100A”.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20220141953 A1) in view of Lee et al. (US 9894764 B2) and Choi et al. (KR 20110104395 A) and Jung et al. (KR 102521788 B1) and in further view of Teck Lee (US 6762503 B2)
Regarding Claim 9 – Jeon in view of Lee, Choi, and Jung teaches the printed circuit board of claim 8, but does not explicitly disclose further comprising: a first pad layer buried by the first solder resist layer; a first additional pad layer disposed within a cutout portion of the first solder resist layer and contacting the first pad layer; and a second additional pad layer disposed on the first additional pad layer.
Teck Lee teaches a first pad layer (Figs 3A-3B, 10A-11D; terminal pad 41) buried by the first solder resist layer (Figs 3A-3B, 10A-11D; solder mask 20, aperture 23; Teck Lee states “metal pad layer that is partially exposed by an aperture in an insulative mask layer” and “Solder mask 20 exposes an area of the terminal pad… by way of aperture 23” and “solder mask 20 defining aperture 23”); a first additional pad layer (Figs 3A-3B, 10A-11D; copper layer 48 / 104) disposed within a cutout portion (Figs 3A-3B, 10A-11D; aperture 23, terminal pad 41) of the first solder resist layer and contacting the first pad layer; and a second additional pad layer disposed on the first additional pad layer (Figs 10A-11D; nickel/gold solderability enhancement layer 18/18a/18b, copper layer 48).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon in view of Lee, Choi, and Jung with a first pad layer buried by the first solder resist layer; a first additional pad layer disposed within a cutout portion of the first solder resist layer and contacting the first pad layer; and a second additional pad layer disposed on the first additional pad layer as taught by Teck Lee because Teck Lee states “the solder ball pad of the present invention also provides increased surface area for solder ball attachment, as well as an indented surface for attachment which may further strengthen the bond” and “provides additional, usable lateral space on the substrate between adjacent solder ball pads for circuit traces and circuit trace spacing”.
Regarding Claim 10 – Jeon in view of Lee, Choi, Jung, and Teck Lee teaches the printed circuit board of claim 9, wherein the cavity further includes a fourth portion defined by a side surface of the second additional pad layer (Figs 3A-3B, 10D-11D; aperture 23, copper layer 48, solderability enhancement layer 18/18a/18b; Tek Lee teaches “a vertical depression consistent with the aperture 23” and that “the solderability enhancement layer 18 may extend onto the vertical side of the copper layer 48”).
Regarding Claim 11 – Jeon in view of Lee, Choi, Jung, and Teck Lee teaches the printed circuit board of claim 10, wherein a width of the fourth portion is different from a first width of the first portion, a second width of the second portion, and a third width of the third portion (Teck Lee; Figs 3A-3B, 10D-11D; aperture 23, solder ball pad layer 60; Teck Lee teaches “the vertical surface of the solder ball mounting pad 36 may be tailored as desired”; also Choi; Figs 2D-2F; Choi [0051, 0056-0057] teaches the different first, second, and third cavity widths). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have tailored the width of Tek Lee’s fourth portion to be different from the first, second, and third widths taught by Choi in order to increase surface area and promote bond strength.
Allowable Subject Matter
Claims 3, 6-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
