CTNF 18/768,907 CTNF 100090 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on July 10, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 4-5, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20220141953 A1) and in further view of Jung et al. (KR 102521788 B1) and Lee et al. (US 9894764 B2) and Choi et al. (KR 20110104395 A) Regarding Claim 1 – Jeon teaches a printed circuit board (Fig 3; PCB 100A), comprising: a first insulating layer (Fig 3; insulating layer 111); a first wiring layer that is buried in the first insulating layer (Fig 3; wiring layer 121; Jeon [0081]); a second insulating layer that is disposed below the first insulating layer (Fig 3; insulating layer 114; Jeon [Claim 16]); a second wiring layer that is buried in the second insulating layer (Fig 3; wiring layer 125; Jeon [Claim 16]). Jeon does not explicitly disclose a first via that is disposed within a first via hole in the first insulating layer; a first solder resist layer that is disposed on the first insulating layer; and a cavity that extends along a height direction by penetrating the first solder resist layer and penetrating a portion of the first insulating layer, wherein the cavity includes a first portion, a second portion, and a third portion having different widths, along the height direction, the first portion is disposed on the second portion and the third portion is disposed on the first portion, and the first via is exposed through the second portion of the cavity. Jung teaches a first via that is disposed within a first via hole in the first insulating layer (Figs 1-2; resin layer 110, through hole T, through electrode 114; Jung [0030, 0034-0036]); and the first via is exposed through the second portion of the cavity (Figs 1-2; cavity C; Jung [0049, 0114]). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon with a first via that is disposed within a first via hole in the first insulating layer; and the first via is exposed through the second portion of the cavity as taught by Jung in order to allow a semiconductor chip to be mounted in the cavity through an exposed conductive connection, Jung [0067] states “The metal bump 230 is stacked on the through electrode 114 exposed by the cavity C” and that “The semiconductor chip 200 is embedded and mounted in the cavity C… via the metal bump 230”. Lee teaches a first solder resist layer that is disposed on the first insulating layer (Fig 2; solder resist layer 270, insulating layer 220); and a cavity that extends along a height direction by penetrating the first solder resist layer and penetrating a portion of the first insulating layer (Fig 2; cavity 271, solder resist layer 270, insulating layer 220; Lee states “the solder resist layer 270… includes a cavity 271 having a through-hole shape” and “The cavity 271 in the solder resist layer 270 exposes a part of the first insulating layer 220 and the first circuit layer 210 to the outside”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon with a first solder resist layer that is disposed on the first insulating layer; and a cavity that extends along a height direction by penetrating the first solder resist layer and penetrating a portion of the first insulating layer as taught by Lee to protect the circuit layer while exposing the needed contact region, Lee states “solder resist layer 270 may be formed so as to cover and protect the first circuit layer 210 from outside, except at the area where the cavity is provided to expose the contact pad 215” and “solder resist layer 270 may prevent the third circuit layer 250 from being damaged due to soldering… may also prevent an oxidation of the third circuit layer 250”. Choi teaches the cavity includes a first portion (Figs 2D-2F; intermediate cavity portion above the second portion at 130), a second portion (Figs 2D-2F; lower narrower cavity portion near 121), and a third portion (Figs 2D-2F; upper wider cavity portion above the first portion at 210) having different widths, along the height direction, the first portion is disposed on the second portion and the third portion is disposed on the first portion (Figs 2D-2F; cavity circuit pattern 121, cavity insulating layer 130, second cavity insulating layer 210; Choi [0051, 0056-0057, 0060-0063]). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon with the cavity includes a first portion, a second portion, and a third portion having different widths, along the height direction, the first portion is disposed on the second portion and the third portion is disposed on the first portion as taught by Choi to improve cavity depth control and avoid “damaging the internal circuit of the cavity in the process of plating, image, etching, etc”. Regarding Claim 4 – Jeon in view of Jung, Lee, and Choi teaches the printed circuit board of claim 1, wherein a first width of the first portion, a second width of the second portion, and a third width of the third portion are different from each other (Choi; Figs 2D-2F; 121, 130, 210; Choi [0051, 0056-0057, 0060-0063] states “the second cavity insulating layer has a shorter length than the first cavity insulating layer” and “a cavity having a structure in which a stepped portion of a cavity is formed and a void space becomes larger as it goes upward can be formed” and “the lower width is narrower than the upper width”). Regarding Claim 5 – Jeon in view of Jung, Lee, and Choi teaches the printed circuit board of claim 4, wherein the second width of the second portion is less than each of the first width of the first portion and the third width of the third portion (Choi; Figs 2D-2F; 121, 130, 210; Choi [0051, 0056-0057, 0060-0063] states “a void space becomes larger as it goes upward can be formed” and “the lower width is narrower than the upper width”). Regarding Claim 8 – Jeon in view of Jung, Lee, and Choi teaches the printed circuit board of claim 1, further comprising: a second via disposed within a second via hole in the second insulating layer (Jung; Figs 1-2; second resin layer 120, second via hole V2, second via electrode 122; Jung [0038, 0041]); a third insulating layer disposed below the second insulating layer (Jung; Figs 1-2; third resin layer 130; Jung [0044]); and a third via disposed within a third via hole in the third insulating layer (Jung; Figs 1-2; third resin layer 130, third via hole V3, third via electrode 132; Jung [0047]) . 07-21-aia AIA Claim (s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20220141953 A1) and in further view of Jung et al. (KR 102521788 B1) and Lee et al. (US 9894764 B2) and Choi et al. (KR 20110104395 A) and in further view of Ko et al. (KR20220136869A) Regarding Claim 2 – Jeon in view of Jung, Lee, and Choi teaches the printed circuit board of claim 1, but does not explicitly disclose wherein the second portion of the cavity is plural in number, and a surface of the first insulating layer between the plurality of second portions included in the cavity has a plurality of protrusions protruding toward the first portion. Ko teaches the second portion of the cavity is plural in number, and a surface of the first insulating layer between the plurality of second portions included in the cavity has a plurality of protrusions protruding toward the first portion (Figs 3-4; first insulating layer 111, first cavity C1, protrusions P; Ko [0008, 0037, 0049, 0054, 0107]). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon in view of Jung, Lee, and Choi with the second portion of the cavity is plural in number, and a surface of the first insulating layer between the plurality of second portions included in the cavity has a plurality of protrusions protruding toward the first portion as taught by Ko because Ko [0041] states “the first cavity C1 and the plurality of protrusions P… facilitate bonding between the electronic component and the printed circuit board 100A” . 07-21-aia AIA Claim (s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20220141953 A1) and in further view of Jung et al. (KR 102521788 B1) and Lee et al. (US 9894764 B2) and Choi et al. (KR 20110104395 A) and in further view of Teck Lee (US 6762503 B2) Regarding Claim 9 – Jeon in view of Jung, Lee, and Choi teaches the printed circuit board of claim 8, but does not explicitly disclose further comprising: a first pad layer buried by the first solder resist layer; a first additional pad layer disposed within a cutout portion of the first solder resist layer and contacting the first pad layer; and a second additional pad layer disposed on the first additional pad layer. Teck Lee teaches a first pad layer (Figs 3A-3B, 10A-11D; terminal pad 41) buried by the first solder resist layer (Figs 3A-3B, 10A-11D; solder mask 20; Teck Lee states “metal pad layer that is partially exposed by an aperture in an insulative mask layer” and “Solder mask 20 exposes an area of the terminal pad… by way of aperture 23” and “solder mask 20 defining aperture 23”); a first additional pad layer (Figs 3A-3B, 10A-11D; copper layer 48 / 104) disposed within a cutout portion (Figs 3A-3B, 10A-11D; aperture 23) of the first solder resist layer and contacting the first pad layer; and a second additional pad layer disposed on the first additional pad layer (Figs 10A-11D; nickel/gold solderability enhancement layer 18). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Jeon in view of Jung, Lee, and Choi with a first pad layer buried by the first solder resist layer; a first additional pad layer disposed within a cutout portion of the first solder resist layer and contacting the first pad layer; and a second additional pad layer disposed on the first additional pad layer as taught by Teck Lee because Teck Lee states “the solder ball pad of the present invention also provides increased surface area for solder ball attachment, as well as an indented surface for attachment which may further strengthen the bond” and “provides additional, usable lateral space on the substrate between adjacent solder ball pads for circuit traces and circuit trace spacing”. Regarding Claim 10 – Jeon in view of Jung, Lee, Choi, and Teck Lee teaches the printed circuit board of claim 9, wherein the cavity further includes a fourth portion (Figs 3A-3B, 7A-7L, 10D-11D; Teck Lee’s additional aperture region around the solder ball pad layer, including aperture 23/terminal aperture 82 area) defined by a side surface of the second additional pad layer (Figs 3A-3B, 7A-7L, 10D-11D; side surface 71). Regarding Claim 11 – Jeon in view of Jung, Lee, Choi, and Teck Lee teaches the printed circuit board of claim 10, wherein a width of the fourth portion is different from a first width of the first portion, a second width of the second portion, and a third width of the third portion (Teck Lee; Figs 3A-3B, 10D, 11D; aperture 23, solder ball pad layer 60, solderability layer 18/18a/18b; Teck Lee teaches the fourth portion width defined by the pad-opening structure; also Choi; Figs 2D-2F; Choi [0051, 0056-0057] teaches the different first, second, and third cavity widths) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3, 6-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA SHARMA whose telephone number is (571)270-7246. The examiner can normally be reached Monday - Friday 8:30 - 5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADITYA SHARMA/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847 Application/Control Number: 18/768,907 Page 2 Art Unit: 2847 Application/Control Number: 18/768,907 Page 3 Art Unit: 2847 Application/Control Number: 18/768,907 Page 4 Art Unit: 2847 Application/Control Number: 18/768,907 Page 5 Art Unit: 2847 Application/Control Number: 18/768,907 Page 6 Art Unit: 2847 Application/Control Number: 18/768,907 Page 7 Art Unit: 2847 Application/Control Number: 18/768,907 Page 8 Art Unit: 2847
Prosecution Insights