DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/25/2024 and 01/23/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 11,398,276 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the current invention is broader than the issued patent. The current application recites similar limitation as the issued patent such as a decoder comprising a first circuit configured to supply a first voltage to the access line, wherein the first circuit comprises: a first transistor configured to supply the first voltage to the access line based at least in part on the first voltage being applied to a source of the first transistor, a ground voltage being applied to a gate of the first transistor, and a threshold voltage of the first transistor; a second transistor configured to isolate the access line based at least in part on the ground voltage being applied to a gate of the second transistor and the second transistor being isolated from one or more voltage sources; and a third transistor configured to isolate the access line based at least in part on the ground voltage being applied to a gate of the third transistor and the ground voltage being applied to a source of the third transistor.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,051,463 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the current invention is broader than the issued patent. The current application recites similar limitation as the issued patent such as a decoder comprising a first circuit configured to supply a first voltage to the access line, wherein the first circuit comprises: a first transistor configured to supply the first voltage to the access line based at least in part on the first voltage being applied to a source of the first transistor, a ground voltage being applied to a gate of the first transistor, and a threshold voltage of the first transistor; a second transistor configured to isolate the access line based at least in part on the ground voltage being applied to a gate of the second transistor and the second transistor being isolated from one or more voltage sources; and a third transistor configured to isolate the access line based at least in part on the ground voltage being applied to a gate of the third transistor and the ground voltage being applied to a source of the third transistor.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanda et al. (US 2007/0201299 A1).
Regarding claim 2, Kanda teaches an apparatus, comprising:
a memory array comprising an access line coupled with a memory cell (Fig. 1, memory array 10); and
a decoder (Fig. 1, Decoder 20) comprising a first circuit configured to supply a first voltage to the access line, wherein the first circuit comprises:
a first transistor configured to supply the first voltage to the access line based at least in part on the first voltage being applied to a source of the first transistor, a ground voltage being applied to a gate of the first transistor, and a threshold voltage of the first transistor (Fig. 16, transistor 152);
a second transistor configured to isolate the access line based at least in part on the ground voltage being applied to a gate of the second transistor and the second transistor being isolated from one or more voltage sources (Fig. 16, second transistor 151); and
a third transistor configured to isolate the access line based at least in part on the ground voltage being applied to a gate of the third transistor and the ground voltage being applied to a source of the third transistor (Fig. 16, third transistor 153).
Regarding claim 3, Kanda further teaches the apparatus of claim 2, wherein the first transistor is configured to supply the first voltage to the access line based at least in part on the first voltage at the source of the first transistor exceeding a sum of the ground voltage at the gate of the first transistor and the threshold voltage of the first transistor (¶0228 to ¶0230).
Regarding claim 4, Kanda further teaches the apparatus of claim 2, wherein the second transistor is configured to isolate the access line based at least in part on a difference between the first voltage and the ground voltage being less than a threshold voltage of the second transistor (Fig. 4, when signal RAD2 is low and a ground voltage is connected to transistor 151, the transistor 151 will isolate the access line WL).
Regarding claim 5, Kanda further teaches the apparatus of claim 2, wherein the second transistor is configured to isolate the access line based at least in part on a source of the second transistor being isolated from the one or more voltage sources (¶0230).
Regarding claim 6, Kanda further teaches the apparatus of claim 5, wherein: the source of the first transistor of the first circuit is coupled with a first transistor of a second circuit of the decoder, the first transistor of the second circuit is configured to provide the first voltage to the first transistor of the first circuit, the source of the second transistor of the first circuit is coupled with a second transistor of the second circuit of the decoder, and the second transistor of the second circuit is configured to isolate the source of the second transistor of the first circuit from the one or more voltage sources (Fig. 18, the transfer gates are connected to other transfer gates using the common lines RDA1 to RAD3).
Regarding claim 7, Kanda further teaches the apparatus of claim 2, wherein the access line is configured to activate the memory cell based at least in part on being supplied with the first voltage (Fig. 16 or Fig. 18, the word lines WLs are using to active the memory cells).
Regarding claim 8, Kanda further teaches the apparatus of claim 2, wherein the first circuit is configured to supply the access line with the first voltage in response to a selection operation, and the first voltage is a positive voltage (Fig. 16, during the selection operation for the word line, the inverter 144 will provide a positive voltage to output RAD1, see ¶0198 and ¶0199).
Regarding claims 9-21, the claims have similar limitations as claims 1-8. Therefore, the claims are rejected under the same grounds of rejection for the same reasoning.
Conclusion
A4ny inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
Prosecution Insights