Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 5/20/2026 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. The Office Action issued in corresponding German application with a May 8, 2026 date was not included.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (“Matsubara”), US 2016/0307854 (listed in the IDS dated 5-20-2026.
Regarding Claim 1, Matsubara discloses a semiconductor device (A1; Fig. 2; ¶ 0034 “semiconductor device A1”) comprising:
an insulating element (12; Fig. 2; ¶ 0034 “an insulating element 12”);
a conductive member (2, 3, 4, 5; Fig. 2; ¶ 0038 “conductive support includes the die pads 2, a plurality of first terminals 3, a plurality of second terminals 4, and a plurality of support terminals 5”) including a first terminal (3, 31, 32; Fig. 2; ¶ 0043 “first terminals 3 include a plurality of first inner terminals 31 and a pair of first outer terminals 32”; ¶ ) and a second terminal (4, 41, 42; Fig. 2; ¶ 0048 “plurality of second terminals 4 include a plurality of second inner terminals 41 and a pair of second outer terminals 42”) that are electrically connected to the insulating element (Fig. 2; ¶ 0077 “first bonding wire 711 electrically connects the control element 111 to at least one of the first terminals 3”; ¶ 0078 “second bonding wires 712 electrically connect the insulating element 12 and the control element 111” therefore the first terminal 3 is electrically connected to the insulating element 12; ¶ 0079 “each third bonding wire 713 is bonded to one of the pads 12a of the insulating element 12 at one end and to one of the pads 112a of the drive element 112 at the other end”; ¶ 0080 “fourth bonding wires 714 provide a conduction path connecting the drive element 112 to the second terminals 4” therefore the second terminal 4 is electrically connected to the insulating element 12);
a sealing resin (6; Figs. 1-3; ¶ 0066 “sealing resin 6”) including a resin first surface (63; Figs. 2-3, 7; ¶ 0068 “pair of first side surfaces 63 of the sealing resin 6”) from which the first terminal protrudes (Figs. 2-3, 7; ¶ 0068 “first terminals 3…are exposed from one of the pair of first side surfaces 63”), and a resin second surface (63; Figs. 2, 4, 7; ¶ 0068 “pair of first side surfaces 63 of the sealing resin 6”) that faces away from the resin first surface (Figs. 2-4, 7; ¶ 0068 “pair of first side surfaces 63 of the sealing resin 6 are spaced apart in the second direction Y and face away from each other”; ¶ 0089 “the first terminals 3 and the second terminals 4 are exposed from a different one of the pair of first side surfaces 63 of the sealing resin 6”) in a first direction (Y; Fig. 2; ¶ 0068 “pair of first side surfaces 63 of the sealing resin 6 are spaced apart in the second direction Y and face away from each other”) perpendicular to a thickness direction (Fig. 7; ¶ 0019 “FIG. 7 is a sectional view along line VII-VII of FIG. 2”; ¶ 0037 “insulating element 12 (also shown in FIG. 7)” therefore a resin second surface 63 is perpendicular to a thickness direction of the insulating element 12) of the insulating element (12; Fig. 7) and from which the second terminal protrudes (Figs. 2, 4, 7; ¶ 0048 “second terminals 4 extend in the second direction Y beyond the other one of the two first side surfaces 63 of the sealing resin 6” and “plurality of second terminals 4 include a plurality of second inner terminals 41 and a pair of second outer terminals 42”; ¶ 0056 “extend in the second direction Y beyond the same first side surface 63 as the second terminals 4, to be partially exposed from the sealing resin 6”); and
a discharge path (Fig. 2; ¶ 0076 “bonding wires 71 connect the first terminals 3, the second terminals 4…to together provide a conduction path within the semiconductor device A1” and “bonding wires 71 include a plurality of first bonding wires 711, a plurality of second bonding wires 712, a plurality of third bonding wires 713, and a plurality of fourth bonding wires 714”; ¶ 0077 “first bonding wire 711 electrically connects the control element 111 to at least one of the first terminals 3”; ¶ 0078 “second bonding wires 712 electrically connect the insulating element 12 and the control element 111”; ¶ 0079 “each third bonding wire 713 is bonded to one of the pads 12a of the insulating element 12 at one end and to one of the pads 112a of the drive element 112 at the other end”; ¶ 0080 “fourth bonding wires 714 provide a conduction path connecting the drive element 112 to the second terminals 4” therefore a discharge path that is a conductive path between the first terminal 3 and the second terminal 4) that is a conductive path (¶ 0076 “provide a conduction path”) between (Fig. 2; ¶ 0076 “bonding wires 71 connect the first terminals 3, the second terminals 4…to together provide a conduction path within the semiconductor device A1”) the first terminal (3, 31, 32) and the second terminal (4, 41, 42).
Matsubara does not specifically disclose a discharge path that is electrically conductive at a voltage lower than a dielectric withstand voltage of the insulating element.
It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention for Matsubara to choose a dielectric with a higher breakdown voltage that will be seen across the discharge path, so the semiconductor device will last longer (have improved reliability).
Regarding Claim 12, Matsubara discloses further comprising:
a control element (111; Fig. 2; ¶ 0035 “control element 111”) electrically connected to the insulating element (Fig. 2; ¶ 0078 “second bonding wires 712 electrically connect the insulating element 12 and the control element 111”); and
a drive element (112; Fig. 2; ¶ 0035 “drive element 112”) electrically connected to the insulating element (Fig. 2; ¶ 0079 “each third bonding wire 713 is bonded to one of the pads 12a of the insulating element 12 at one end and to one of the pads 112a of the drive element 112 at the other end”).
Regarding Claim 13, Matsubara discloses wherein the conductive member (2) includes:
a first die pad (21; Fig. 2; ¶ 0039 “die pads 2 includes the first die pad 21 and the second die pad 22”) on which the control element is mounted (Fig. 2; ¶ 0037 “control element 111…mounted on a first die pad 21, which is one of die pads 2”); and
a second die pad (22; Fig. 2; ¶ 0039 “die pads 2 includes the first die pad 21 and the second die pad 22”) spaced apart from the first die pad (Fig. 2; ¶ 0039 “shown in FIG. 2, the first die pad 21 is spaced apart from the second die pad 22 in the second direction Y”) and on which the drive element is mounted (Fig. 2; ¶ 0037 “drive element 112 is mounted on a second die pad 22, which is another one of the die pads 2”).
Regarding Claim 14, Matsubara discloses wherein the insulating element is mounted on the first die pad (Fig. 2; ¶ 0037 “insulating element 12 are mounted on a first die pad 21, which is one of die pads 2”).
Allowable Subject Matter
Claims 2-11 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the prior art does not teach or render obvious further comprising a discharge portion exposed from the sealing resin and insulated from the conductive member, wherein the discharge path includes the discharge portion and a path formed by creeping discharge at a surface of the sealing resin between the discharge portion and each of the first terminal and the second terminal. Therefore, the combination of the features of Claims 1 and 2 is considered allowable.
Claims 3-11 incorporate all of the limitations of Claim 2. Therefore, they are also allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 15, the prior art does not teach or render obvious wherein the conductive member further includes a third die pad spaced apart from the first die pad and the second die pad and on which the insulating element is mounted. Therefore, the combination of the features of Claims 1, 12, 13, and 15 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Osada et al, US 2015/0137314, discloses a semiconductor device having an insulating element, a first terminal, a second terminal, and a sealing resin. Kikuchi, US 2021/0265310, discloses a semiconductor device having an insulating element, a first terminal, a second terminal, and a sealing resin.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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