DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2018-174175 Japan 09/18/2018).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 07/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 07/10/2024. These drawings are review and accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-17 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-12 of U.S Patent No. 12,068,044 B2 (‘044). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘044 claims.
US Patent No. 12,068,044 B2
US Patent Application No. 2024/0363175 A1
1. A memory system comprising: a semiconductor memory including memory cells and a word line coupled to the memory cells, each of the memory cells being capable of storing four-bit data, and a controller configured to: read a first data item from the memory cells through application of a first voltage to the word line; repeat a first operation to read first bit data in each of the memory cells, the first operation including applying a second voltage to the word line, the first operation including applying a third voltage to the word line after applying the second voltage, the third voltage having a magnitude different from that of the second voltage, the second voltage being changed within a first range every time the first operation is repeated, the third voltage being changed within a second range every time the first operation is repeated; read a plurality of second data items by the repeating of the first operation; and mask part of each of the second data items using the first data item.
2. The system of claim 1, wherein: the first voltage has a magnitude between a magnitude of the second voltage and a magnitude of the third voltage.
3. The system of claim 2, wherein: the controller is further configured to: obtain a plurality of third data items through the masking with the first data item; and determine a first read voltage within the first range and a second read voltage within the second range based on the third data items.
4. The system of claim 3, wherein: the controller is further configured to apply a first read voltage and a second read voltage to the word line to read data stored in the memory cells.
5. The system claim 1, wherein: the controller is further configured to determine the first range based on the word line.
6. The system claim 5, wherein: the controller is further configured to determine the second range based on the word line.
7. The system of claim 1, wherein: the controller is further configured to: determine in which one of two states each of the memory cells is, based on the first voltage, to obtain the first data item; and determine in which one of sixteen states each of the memory cells is to obtain one of the second data items.
8. The system of claim 7, wherein: the first data item includes a plurality of first bits, each of the first bits is based on in which one of two states one of the memory cells is, based on the first voltage, each of the memory cells is capable of storing data in a first digit bit, a second digit bit, a third digit bit, and a fourth digit bit, each of the second data items includes a plurality of second bits, and each of the second bits of one of the second data items includes a data stored in the first digit bit of one of the memory cells.
9. The system of claim 1, wherein: the controller is further configured to perform a logical operation on one of the second data items and the first data item to mask the one of the second data items.
10. The system of claim 1, wherein: the controller is further configured to: obtain a plurality of third data items through the masking with the first data item; determine a plurality of first counts of memory cells estimated to have threshold voltages respectively corresponding to a plurality of voltages within the first range based on the third data items; and detect, from the first counts, one or two or more second counts that are local minimum within the first range.
11. The system of claim 10, wherein the controller is further configured to: select, when the two or more second counts are detected, a third count from the two or more second counts that are nearest to a number of the memory cells×Y/16 (wherein Y is a natural number not larger than 16), and use a voltage corresponding to the third count to determine whether a threshold voltage of one of the memory cells is higher than a Yth lowest boundary voltage of fifteen boundary voltages.
12. The system of claim 5, wherein: the controller is further configured to select the first voltage based on the first range.
1. A method of controlling a semiconductor memory including memory cells and a word line coupled to the memory cells, each of the memory cells being capable of storing four-bit data, the method comprising: reading a first data item from the memory cells through application of a first voltage to the word line; repeating a first operation to read first bit data in each of the memory cells, the first operation including applying a second voltage to the word line, and applying a third voltage to the word line, the third voltage having a magnitude different from that of the second voltage, the second voltage being changed within a first range every time the first operation is repeated, the third voltage being changed within a second range every time the first operation is repeated; reading a plurality of second data items by the repeating of the first operation; and masking part of each of the second data items using the first data item, wherein a number of repeating the first operation is greater than or equal to four.
2. The method of claim 1, wherein: the first voltage has a magnitude between a magnitude of the second voltage and a magnitude of the third voltage.
3. The method of claim 2, further comprising: obtaining a plurality of third data items through the masking with the first data item; and determining a first read voltage within the first range and a second read voltage within the second range based on the third data items.
4. The method of claim 3, further comprising: applying a first read voltage and a second read voltage to the word line to read data stored in the memory cells.
5. The method of claim 1, further comprising: determining the first range based on the word line.
6. The method of claim 5, further comprising: determining the second range based on the word line.
7. The method of claim 1, further comprising: determining in which one of two states each of the memory cells is, based on the first voltage, to obtain the first data item; and determining in which one of sixteen states each of the memory cells is to obtain one of the second data items.
8. The method of claim 7, wherein: the first data item includes a plurality of first bits, each of the first bits is based on in which one of two states one of the memory cells is, based on the first voltage, each of the memory cells is capable of storing data in a first digit bit, a second digit bit, a third digit bit, and a fourth digit bit, each of the second data items includes a plurality of second bits, and each of the second bits of one of the second data items includes a data stored in the first digit bit of one of the memory cells.
9. The method of claim 1, further comprising: performing a logical operation on one of the second data items and the first data item to mask the one of the second data items.
10. The method of claim 1, wherein: each of the memory cells is capable of storing four-bit data storing four-bit data by correlating the four-bit data with first to sixteenth threshold voltage regions.
11. The method of claim 10, wherein: the first voltage is a boundary voltage between the i-th threshold voltage region and the (i+1)-th threshold voltage region, i is an integer greater than or equal to two, and i is an integer smaller than 15, the second voltage is a boundary voltage between the j-th threshold voltage region and the (j+1)-th threshold voltage region, j is an integer greater than or equal to one, and j is an integer smaller than 14, the third voltage is a boundary voltage between the k-th threshold voltage region and the (k+1)-th threshold voltage region, k is an integer greater than or equal to three, and k is an integer smaller than 16, i is greater than j, and k is greater than i.
12. The method of claim 11, wherein: the first read level is between the eleventh threshold voltage region and the twelfth threshold voltage region.
13. The method of claim 1, further comprising: obtaining a plurality of third data items through the masking with the first data item; determining a plurality of first counts of memory cells estimated to have threshold voltages respectively corresponding to a plurality of voltages within the first range based on the third data items; and detecting, from the first counts, one or two or more second counts that are local minimum within the first range.
14. The method of claim 13, wherein: the number of repeating of the first operation is greater than or equal to five, the method further comprises: selecting, when the two or more second counts are detected, a third count from the two or more second counts that are nearest to a number of the memory cells×Y/16 (wherein Y is a natural number not larger than 16).
15. The method of claim 14, further comprising: using a voltage corresponding to the third count to determine whether a threshold voltage of one of the memory cells is higher than a Y-th lowest boundary voltage of fifteen boundary voltages.
16. The method of claim 5, further comprising: selecting the first voltage based on the first range.
17. The method of claim 1, wherein: in the first operation, the third voltage is applied to the word line after the second voltage is applied to the word line.
Allowable Subject Matter
Claims 1-17 are presently rejected under obviousness double patenting, but would be allowable provided that a terminal disclaimer is filed.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 01/06/2026