DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tien et al. (US 20220075923 A1) hereinafter referred to as "Tien".
Regarding claim 1, Tien teaches a semiconductor device comprising: cell regions (Fig 1, element 104; ¶: [0022]) arranged in rows which extend substantially in a first direction, each row of the rows includes at least one instance of a first cell region or a second cell region (Fig 1, element 104; ¶: [0022]), each of the first cell region and the second cell region including: structures in a transistor layer (Fig 5, element 560; ¶: [0088, 0093]); conductive segments in a first metallization layer (M_1st layer) (Fig 3, element 302, 304 ; ¶: [0056, 0025]) over the transistor layer, the conductive segments in the M_1st layer extending substantially in the first direction (Fig 3, element 302, 304; ¶: [0056, 0025]), relative to a second direction substantially perpendicular to the first direction, the M_1st layer having a first pitch as a sole pitch (Fig 3, element P_PG(1); ¶: [0056, 0029]), the first pitch being for the conductive segments of the M_1st layer; conductive segments in a second metallization layer (M_2nd layer) (Fig 5, element 562; ¶: [0088, 0090]); and conductive segments in a third metallization layer (M_3rd layer) (Fig 2A, 2B, element 202, 204, 206; ¶: [0025]) over the M_1st layer, the conductive segments in the M_3rd layer extending substantially in the first direction and including conductive segments for a power grid (PG segments) (Fig 2, element 202, 204; ¶: [0025]) and conductive segments for control or data signals (logic segments) (Fig 2, element 206; ¶: [0025]), relative to the second direction, the M_3rd layer having multiple pitches including: a second pitch (Fig 2, element p_rte; ¶: [0033]) for the logic segments; and a third pitch (Fig 2, element P_PG(1); ¶: [0029]) for the PG segments, the third pitch being greater than the second pitch, and the second pitch being different from the first pitch.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 7-9, 14,18 are rejected under 35 U.S.C. 103 as being unpatentable over Tien et al. (US 20220075923 A1) hereinafter referred to as "Tien" in view of Sue et al. (US 20200134124) hereinafter referred to as "Sue".
Regarding claim 2, Tien teaches the semiconductor device of claim 1. Tien does not teach each of the structures in the transistor layer including gate patterns extending in the second direction, the gate patterns crossing active areas that extend in the first direction.
Sue teaches each of the structures in the transistor layer including gate patterns extending in the second direction, the gate patterns crossing active areas that extend in the first direction (Fig.2I(2), element 232; ¶: [0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include gate patterns in order to represent a contacted poly pitch of a corresponding semiconductor process technology node (Sue, ¶: [0095]).
Regarding claim 7, Tien teaches a semiconductor device comprising: cell regions (Fig 1,2, element 104, 201A; ¶: [0022]) arranged in rows extending in a first direction, each of the rows having a row height in a second direction perpendicular to the first direction (Fig. 1, 2, element 104, 201A, row(k, k+1); ¶: [0022, 0028]), each row of the rows includes at least one instance of a first cell region or a second cell region (Fig 1, element 104; ¶: [0022]), each of the first cell region and the second cell region including: a transistor layer (Fig 5, element 560; ¶: [0088, 0093]); conductive segments extending in the first direction in a first metallization (M_1st) (Fig 3, element 302, 304 ; ¶: [0056, 0025]) layer that overlaps the transistor layer in a third direction, the conductive segments in the M_1st layer including: first M_1st conductive segments (Fig 3, element 302, 304; ¶: [0056, 0025]) configured for a power grid; and second M_1st conductive segments (Fig 3, element track(j) ; ¶: [0056, 0063]) configured for at least one of control or data signals, wherein, relative to the second direction, conductive segments extending in the second direction in a second metallization (M_2nd) (Fig 5, element 562; ¶: [0088, 0090]) layer over the M_1st layer; and conductive segments extending in the first direction in a third metallization (M_3rd) (Fig 2A, 2B, element 202, 204, 206; ¶: [0025]) layer over the M_2nd layer, the conductive segments in the M_3rd layer including: first M_3rd conductive segments (Fig 2A, 2B, element 202, 204; ¶: [0025]) configured for the power grid; and second M_3rd conductive segments (Fig 2A, 2B, element 206; ¶: [0025]) configured for at least one of control or data signals, wherein, relative to the second direction, the first M_3rd conductive segments have a different height from the second M_3rd conductive segments (Fig 2A, 2B, element 202, 204, 206; ¶: [0025]). Tien does not, however, teach the first M_1st conductive segments having a same height as the second M_1st conductive segments.
Sue teaches the first M_1st conductive segments having a same height as the second M_1st conductive segments (Fig. 2A, element 205; ¶: [0020])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to _have a set of conductive segments be a first pitch in accordance with the rules and scale of the corresponding semiconductor process technology node (Sue, ¶: [0020]).
Regarding claim 8, Tien in view of Sue teaches the semiconductor device of claim 7. Tien further teaches the M_1st layer having a first pitch as a sole pitch for the first M_1st conductive segments and the second M_1st conductive segments (Fig 3, element P_PG(1); ¶: [0056, 0029]), the M_3rd layer having multiple pitches, including: a second pitch (Fig 2, element P_PG(1); ¶: [0029]) for the first M_3rd conductive segments; and a third pitch (Fig 2, element p_rte; ¶: [0033])for the second M_3rd conductive segments, the first pitch being different from the third pitch, and the second pitch being greater than the third pitch (Fig 2, element P_PG(1), p_rte; ¶: [0029]).
Regarding claim 9, Tien in view of Sue teaches the semiconductor device of claim 7. Tien does not teach the transistor layer including gate patterns extending in the second direction, the gate patterns crossing active areas that extend in the first direction.
Sue teaches the transistor layer including gate patterns extending in the second direction, the gate patterns crossing active areas that extend in the first direction. (Fig.2I(2), element 232; ¶: [0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include gate patterns in order to represent a contacted poly pitch of a corresponding semiconductor process technology node (Sue, ¶: [0095]).
Regarding claim 14, Tien teaches A semiconductor device comprising: a transistor layer (Fig 5, element 560; ¶: [0088, 0093]); conductive segments extending in a first direction in a first metallization (M_1st) (Fig 3, element 302, 304 track(j); ¶: [0056, 0025, 0063]) layer that overlaps the transistor layer, the conductive segments in the M_1st layer including: first M_1st conductive segments (Fig 3, element 302, 304; ¶: [0056, 0025]) configured for a power grid; and second M_1st conductive segments (Fig 3, element track(j) ; ¶: [0056, 0063]) configured for at least one of control or data signals, wherein, relative to a second direction perpendicular to the first direction; conductive segments extending in the second direction in a second metallization (M_2nd) (Fig 5, element 562; ¶: [0088, 0090]) layer over the M_1st layer; and conductive segments extending in the first direction in a third metallization (M_3rd) (Fig 2A, 2B, element 202, 204, 206; ¶: [0025]) layer over the M_2nd layer, the conductive segments in the M_3rd layer including: first M_3rd conductive segments (Fig 2A, 2B, element 202, 204; ¶: [0025]) configured for the power grid; and second M_3rd conductive segments Fig 2A, 2B, element 206; ¶: [0025]) configured for at least one of control or data signals, wherein, relative to the second direction, the first M_3rd conductive segments have a different height from the second M_3rd conductive segments (Fig 2A, 2B, element 202, 204, 206; ¶: [0025]).
Tien does not teach the first M_1st conductive segments having a same height as the second M_1st conductive segments.
Sue teaches the first M_1st conductive segments having a same height as the second M_1st conductive segments (Fig. 2A, element 205; ¶: [0020])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to _have a set of conductive segments be a first pitch in accordance with the rules and scale of the corresponding semiconductor process technology node (Sue, ¶: [0020]).
Regarding claim 15, Tien in view of Sue teaches the semiconductor device of claim 14. Tien further teaches the first M_3rd conductive segments having a greater height than the second M_3rd conductive segments (Fig 2A, 2B, element 202, 204, 206; ¶: [0025] Tien).
Regarding claim 16, Tien in view of Sue teaches the semiconductor device of claim 14. Tien further teaches the first M_3rd conductive segments having a greater height than the second M_3rd conductive segments, and a greater height than the first and second M_1st conductive segments (Fig 2, 3, element SA(1), SB(1); ¶: [0031] Tien)
Regarding claim 17, Tien in view of Sue teaches the semiconductor device of claim 14. Tien further teaches the M_1st layer having a first pitch as a sole pitch for the first M_1st conductive segments and the second M_1st conductive segments (Fig 3, element P_PG(1); ¶: [0056, 0029] Tien), the M_3rd layer having multiple pitches, including: a second pitch (Fig 2, element P_PG(1); ¶: [0029] Tien) for the first M_3rd conductive segments; and a third pitch (Fig 2, element p_rte(1); ¶: [0033] Tien) for the second M_3rd conductive segments, the first pitch being different from the third pitch, and the second pitch being greater than the third pitch (Fig 2, element P_PG(1), p_rte; ¶: [0029] Tien).
Regarding claim 18, Tien in view of Sue teaches the semiconductor device of claim 14. Tien does not teach the transistor layer including gate patterns extending in the second direction, the gate patterns crossing active areas that extend in the first direction.
Sue teaches the transistor layer including gate patterns extending in the second direction, the gate patterns crossing active areas that extend in the first direction (Fig.2I(2), element 232; ¶: [0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include gate patterns in order to represent a contacted poly pitch of a corresponding semiconductor process technology node (Sue, ¶: [0095]).
Allowable Subject Matter
Claims 3-6, 10-13, and 19-20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3-4 are objected to due to their dependence on claim 2
Claims 5-6 are objected to due to their dependence on claim 1
Claims 10 is objected to due to its dependence on claim 9
Claims 11-13 are objected to due to their dependence on claim 7
Claims 19-20 are objected to due to their dependence on claim 18
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 U.S.C. 112:
Regarding claim 3, Tien in view of Sue teaches specific elements of the claimed invention including a combination row that includes a first cell region and a second cell region. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “active areas in the first cell region having a first height in the second direction, and active areas in the second cell region having a second height in the second direction, the second height being different from the first height”.
Regarding claim 4, Tien in view of Sue teaches specific elements of the claimed invention including a combination row that includes a first cell region and a second cell region. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “the first height is greater than the second height, the first cell region is a high-power cell region, and the second cell region is a low-power cell region”.
Regarding claim 5, Tien teaches specific elements of the claimed invention including a combination row that includes a first cell region and a second cell region. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “the first row having a first row height, the second row having a second row height, and the first row height is greater than the second row height”.
Regarding claim 6, Tien teaches specific elements of the claimed invention including a combination row that includes a first cell region and a second cell region. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “a third row of the rows is a second-cell-region-only row, the third row having a third row height in the second direction, and the first row height is equal to a sum of the first row height and the third row height”.
Regarding claim 10, Tien in view of Sue teaches specific elements of the claimed invention including a combination row that includes a first cell region and a second cell region. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “active areas in the first cell region have a first height in the second direction, and active areas in the second cell region have a second height in the second direction, the second height being different from the first height”.
Regarding claim 11, Tien in view of Sue teaches specific elements of the claimed invention including rows including a first row and a second row, the second row being adjacent to the first row. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “a first instance of the first cell region stacked on a first instance of the second cell region such that the first instance of the first cell region is between the first row and the first instance of the second cell region; and a second instance of the second cell region stacked on a second instance of the first cell region such that the second instance of the second cell region is between the first row and the second instance of the first cell region”.
Regarding claim 12, Tien in view of Sue teaches specific elements of the claimed invention including rows including a first row and a second row, the second row being adjacent to the first row. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “the first height of the first cell region being different than the second height of the second cell region”.
Regarding claim 19, Tien in view of Sue teaches specific elements of the claimed invention including one row of the rows being a combination row that includes a first cell region and a second cell region. However, the prior art, when taken alone or in combination to the examiner’s knowledge cannot be construed as teaching or suggesting all of the elements of the claimed invention, specifically regarding “active areas in the first cell region having a first height in the second direction, and active areas in the second cell region having a second height in the second direction, the second height being different from the first height”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IHSAN HAWKINS whose telephone number is (571)272-8594. The examiner can normally be reached Mon-Thu 7:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/I.H./ Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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