DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 14-16 and 18-19 are rejected under 35 U.S.C. §103 as being unpatentable over Momo et al. U.S. Patent Application Publication 2019/0157262 (the ‘262 reference) in view of Moroz et al. U.S. Patent 10,037,397 B2.
The ‘262 reference discloses in Figs. 4 and 11B, para [83] (paragraph(s) [0083]) and other text an integrated circuit layout as claimed, but does not disclose a non-transitory computer-readable medium.
Moroz, in disclosing an integrated circuit layout, teaches a non-transitory computer-readable medium for storing the integrated circuit layout (col. 31, lines 4-21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have stored the reference’s integrated circuit layout in a non-transitory computer-readable medium. One would have been motivated to make such a utility in view of the teachings in Moroz for, for example, safekeeping purpose.
Thus, such a modification would have resulted in:
referring to claim 14, an integrated circuit (IC) layout stored on a non-transitory computer-readable medium (as taught by Moroz), the layout comprising:
an active region (660, para [202]);
a first contact region (706) over a first portion of the active region;
a second contact region (“second contact region”, label added by the examiner for ease of explanation, Fig. 4 reproduced below) over a second portion of the active region;
a first via (703) over the first contact region (706);
a second via (“second via”) over the second contact region (the “second contact region”);
a first conductive pattern (“first conductive pattern”, comprising wiring 707) over the first via (703) and the second via (the “second via”);
a first through via (702) under the first portion of the active region;
a second through via (“second through via”) under the second portion of the active region; and
a second conductive pattern (“second conductive pattern”) under the first through via and the second through via;
referring to claim 15, wherein the first conductive pattern (the “first conductive pattern”) is in a metal layer (wiring layer) which may be termed “a metal-zero layer”, and the second conductive pattern (the “second conductive pattern”) is in a back side metal layer (wiring layer in the back side of the active region 660), which may be termed a “back side metal-zero layer”;
referring to claim 16, wherein the first conductive pattern (the “first conductive pattern”) has a width (a width of “707-3”, see Fig. 4 below) smaller than a width (a width of “705-5”) of the second conductive pattern (the “second conductive pattern”);
referring to claim 18, a gate region (674, Fig. 11B, para [202, 206]), which may be termed a “dummy gate region”, arranged between the first portion and the second portion of the active region (660);
and
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referring to claim 19, wherein the dummy gate region (674) is immediately adjacent to at least one of the first portion or the second portion of the active region (660).
Allowable Subject Matter
3. Claims 1- 10 are allowable over the prior art of record.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an integrated circuit (IC) device and an integrated circuit (IC) layout stored on a non-transitory computer-readable medium with all exclusive limitations as recited in claims 1, 17 and 20, which may be characterized (claim 1) in that a first terminal of the first transistor is electrically coupled to a second terminal of the second transistor both over the first side of the substrate and under the second side of the substrate, (claim 17) at least one of the first contact region has an area smaller than an area of the first through via, or the second contact region has an area smaller than an area of the second through via, and (claim 20) in that each of the first through via and the second through via has a larger area than a corresponding one of the first contact region and the second contact region.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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08-13-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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