DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 7/10/2024 and 5/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH RESISTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME.
Claims Status
Claims 1-20 are currently pending and being examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 9-11; 12-14, 17-19; and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal et al (US 2016/0218062 A1, hereafter Aggarwal) in view of Chu et al (US 4,682,143 A, hereafter Chu).
Re claim 1, Aggarwal discloses in FIG. 3 a semiconductor device (300) comprising:
a first dielectric film (314; [0038]);
a resistor element (324; [0040]) disposed on the first dielectric film (314), the resistor element (320) containing silicon (as in 124; [0016] and [0040]), chromium (as in 124; [0016] and [0040]), and carbon (as in 124; [0016] and [0040]); and
a second dielectric film (328; [0041]) disposed on the resistor element (324) so as to contact (physically touch) the resistor element (324).
Aggarwal fails to disclose wherein a silicon concentration of the resistor element (324) increases from a center part of the resistor element (324) towards an upper surface of the resistor element (324), and increases from the center part of the resistor element (324) towards a lower surface of the resistor element (324).
However,
Chu discloses in FIG. 1 a resistor element (thin film chromium-silicon-carbon resistor material; col. 3, lines 5-9 and 30-68) disposed on a first dielectric film (silicon oxide), the resistor element (thin film chromium-silicon-carbon resistor material) containing silicon (col. 3, lines 30-46), chromium (col. 3, lines 30-46), and carbon (col. 3, lines 30-46).
Chu further discloses the resistor element (thin film chromium-silicon-carbon resistor material) has overlapping chromium wt. %, silicon wt. %, and silicon wt. %, and annealed at an overlapping temperature range (FIG. 1), capable of being configured (MPEP § 2144.05) in a substantially identical structure (MPEP § 2112.01 and § 2112.02) as the claimed invention, and would be expected to exhibit the same characteristics of a silicon concentration of the resistor element (324) increases from a center part of the resistor element (324) towards an upper surface of the resistor element (324), and increases from the center part of the resistor element (324) towards a lower surface of the resistor element (324), as claimed to establish a prima facie case of obviousness to provide an improved thin film resistor material with an acceptable resistivity, a low temperature coefficient of resistance, and good absolute and matching stability over lifetime, which is annealable at a temperature sufficiently above other subsequent processing temperatures utilized in constructing an integrated circuit structure containing the resistor material to avoid altering of the resistor film characteristics after annealing, and having a temperature coefficient of expansion which will be compatible with that of silicon oxide substrate materials (Chu; col. 2, lines 23-43).
Re claims 2-3, Aggarwal discloses the semiconductor device according to claim 1.
But, fails to disclose wherein a chromium concentration of the resistor element (324) decreases from the center part of the resistor element (324) towards the upper surface of the resistor element (324), and decreases from the center part of the resistor element (324) towards the lower surface of the resistor element (324); and wherein a carbon concentration of the resistor element (324) increases from the center part of the resistor element (324) towards the upper surface of the resistor element (324), and increases from the center part of the resistor element (324) towards the lower surface of the resistor element (324).
However, Chu discloses the resistor element (thin film chromium-silicon-carbon resistor material) has overlapping chromium wt. %, silicon wt. %, and silicon wt. %, and annealed at an overlapping temperature range (FIG. 1), capable of being configured (MPEP § 2144.05) in a substantially identical structure (MPEP § 2112.01 and § 2112.02) as the claimed invention, and would be expected to exhibit the same characteristics of a chromium concentration of the resistor element (324) decreases from the center part of the resistor element (324) towards the upper surface of the resistor element (324), and decreases from the center part of the resistor element (324) towards the lower surface of the resistor element (324); and wherein a carbon concentration of the resistor element (324) increases from the center part of the resistor element (324) towards the upper surface of the resistor element (324), and increases from the center part of the resistor element (324) towards the lower surface of the resistor element (324), as part of the improved thin film resistor material discussed for claim 1.
Re claim 4, Aggarwal discloses the semiconductor device according to claim 1, wherein a thickness of the resistor element (324) is 10 nm or less (less than 15 nm; [0016] and [0040]).
Re claim 5, Aggarwal and Chu disclose the semiconductor device according to claim 4, wherein a ratio of silicon to chromium is greater than 2, and wherein a carbon content in the resistor element is 15 atomic percent or more and 30 atomic percent or less (see claims 1-3), as part of the improved thin film resistor material discussed for claim 1.
Re claims 9-10, Aggarwal and Chu disclose the semiconductor device according to claim 1, wherein in the resistor element, a silicon concentration in a region close to a side surface of the resistor element is higher than a silicon concentration in the center part of the resistor element (see claims 1-3 and 5); and wherein in the resistor element, a chromium concentration in the region close to the side surface of the resistor element is lower than a chromium concentration in the center part of the resistor element, and wherein in the resistor element, a carbon concentration in the region close to the side surface of the resistor element is higher than a carbon concentration in the center part of the resistor element (see claims 1-3 and 5), as part of the improved thin film resistor material discussed for claim 1.
Re claim 11, Aggarwal discloses the semiconductor device according to claim 1, comprising: a first wiring (left 392; [0037]) disposed so as to be covered by (below) the first dielectric film (314); a second wiring (right 392; [0037]) disposed so as to be covered by (below) the first dielectric film (314); a first plug (left 322; [0039]) disposed in the first dielectric film (314) and connected to the first wiring (left 392); and a second plug (right 322; [0039]) disposed in the first dielectric film (314) and connected to the second wiring (right 392; [0037]), wherein the resistor element (324) connects ([0040]) the first plug (left 322) and the second plug (right 322).
Re claim 12, Aggarwal discloses in FIGS. 4A-4G a method of manufacturing a semiconductor device, the method comprising:
(a) forming a first dielectric film (314 in FIG. 4D; [0049]);
(b) forming a resistor element (324 in FIG. 4F; [0053]) on the first dielectric film (314), the resistor element (324) containing silicon (as in 124; [0016] and [0053]), chromium (as in 124; [0016] and [0053]), and carbon (as in 124; [0016] and [0053]);
(c) forming a second dielectric film (328 in FIG. 4F; [0053]) on the first dielectric film (314) so as to cover the resistor element (324) and contact (physically touch) the resistor element (324).
Aggarwal fails to disclose and (d) after the (c), performing an annealing treatment on the resistor element in a state where the second dielectric film is disposed on the resistor element, wherein a silicon concentration of the resistor element after the (d) increases from a center part of the resistor element towards an upper surface of the resistor element, and increases from the center part of the resistor element towards a lower surface of the resistor element.
However,
Chu discloses in FIG. 1 a resistor element (thin film chromium-silicon-carbon resistor material; col. 3, lines 5-9 and 30-68) method formed on a first dielectric film (silicon oxide), the resistor element (thin film chromium-silicon-carbon resistor material) containing silicon (col. 3, lines 30-46), chromium (col. 3, lines 30-46), and carbon (col. 3, lines 30-46).
Chu further discloses the resistor element (thin film chromium-silicon-carbon resistor material) has overlapping chromium wt. %, silicon wt. %, and silicon wt. %, and annealed at an overlapping temperature range (FIG. 1), capable of being configured (MPEP § 2144.05) in a substantially identical structure (MPEP § 2112.01 and § 2112.02) as the claimed invention, and would be expected to exhibit the same characteristics of a silicon concentration of the resistor element after the (d) increases from a center part of the resistor element towards an upper surface of the resistor element, and increases from the center part of the resistor element towards a lower surface of the resistor element, as claimed to establish a prima facie case of obviousness, by (d) after the (c) of performing an annealing treatment on the resistor element in a state where the second dielectric film is disposed on the resistor element, to provide an improved thin film resistor material with an acceptable resistivity, a low temperature coefficient of resistance, and good absolute and matching stability over lifetime, which is annealable at a temperature sufficiently above other subsequent processing temperatures utilized in constructing an integrated circuit structure containing the resistor material to avoid altering of the resistor film characteristics after annealing, and having a temperature coefficient of expansion which will be compatible with that of silicon oxide substrate materials (Chu; col. 2, lines 23-43).
Re claim 13, Aggarwal discloses the method according to claim 12, wherein the (b) comprises: (b1) forming a first film (354 in FIG. 4E; [0050]) on the first dielectric film (314), the first film (354) containing silicon (as in 124; [0016] and [0053]), chromium (as in 124; [0016] and [0053]), and carbon (as in 124; [0016] and [0053]); and (b2) after the (b1), patterning (with 360 in FIG. 4F; [0053]) the first film (354) to form the resistor element (324).
Re claim 14, Aggarwal and Chu disclose the method according to claim 12, wherein a temperature of the annealing treatment is 300 degrees Celsius or more and 500 degrees Celsius or less (Chu: FIG. 1), as part of the method for improved thin film resistor material discussed for claim 12.
Re claim 17, Aggarwal discloses the method according to claim 12, wherein a thickness of the resistor element (324) is 10 nm or less (less than 15 nanometers; [0050]).
Re claims 18-19, Aggarwal and Chu disclose the method according to claim 12, wherein a chromium concentration of the resistor element after the (d) decreases from the center part of the resistor element towards the upper surface of the resistor element, and decreases from the center part of the resistor element towards the lower surface of the resistor element (see claims 1-3; and 12); and wherein a carbon concentration of the resistor element after the (d) increases from the center part of the resistor element towards the upper surface of the resistor element, and increases from the center part of the resistor element towards the lower surface of the resistor element (see claims 1-3; and 12).
Re claim 20, Aggarwal discloses in FIGS. 4A-4G a method of manufacturing a semiconductor device, the method comprising:
(a) forming a first dielectric film (314 in FIG. 4D; [0049]);
(b) forming a first film (354 in FIG. 4E; [0050]) on the first dielectric film (314), the first film (354) containing silicon (as in 124; [0016] and [0053]), chromium (as in 124; [0016] and [0053]), and carbon (as in 124; [0016] and [0053]);
(c) forming a second dielectric film (356 in FIG. 4E; [0051]) film (354) on the first film (354) so as to contact (physically touch) the first film (354);
(d) after the (c), patterning (with 360 in FIG. 4F; [0053]) the second dielectric film (356) and the first film (354) to form a resistor element (324) from the patterned first film ([0053]).
Aggarwal fails to disclose and (e) after the (c), performing an annealing treatment on the first film or on the resistor element in a state where the second dielectric film is disposed on the first film or on the resistor element, wherein a silicon concentration of the resistor element after the (c) increases from a center part of the resistor element towards an upper surface of the resistor element, and increases from the center part of the resistor element towards a lower surface of the resistor element.
However,
Chu discloses in FIG. 1 a resistor element (thin film chromium-silicon-carbon resistor material; col. 3, lines 5-9 and 30-68) method formed on a first dielectric film (silicon oxide), the resistor element (thin film chromium-silicon-carbon resistor material) containing silicon (col. 3, lines 30-46), chromium (col. 3, lines 30-46), and carbon (col. 3, lines 30-46).
Chu further discloses the resistor element (thin film chromium-silicon-carbon resistor material) has overlapping chromium wt. %, silicon wt. %, and silicon wt. %, and annealed at an overlapping temperature range (FIG. 1), capable of being configured (MPEP § 2144.05) in a substantially identical structure (MPEP § 2112.01 and § 2112.02) as the claimed invention, and would be expected to exhibit the same characteristics of a silicon concentration of the resistor element after the (c) increases from a center part of the resistor element towards an upper surface of the resistor element, and increases from the center part of the resistor element towards a lower surface of the resistor element, as claimed to establish a prima facie case of obviousness, by (e) after the (c) of performing an annealing treatment on the first film or on the resistor element in a state where the second dielectric film is disposed on the first film or on the resistor element, to provide an improved thin film resistor material with an acceptable resistivity, a low temperature coefficient of resistance, and good absolute and matching stability over lifetime, which is annealable at a temperature sufficiently above other subsequent processing temperatures utilized in constructing an integrated circuit structure containing the resistor material to avoid altering of the resistor film characteristics after annealing, and having a temperature coefficient of expansion which will be compatible with that of silicon oxide substrate materials (Chu; col. 2, lines 23-43).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal and Chu as applied to claim 4 above, and further in view of JESSEN et al (US 2024/0113156 A1, hereafter Jessen).
Re claims 6-7, Aggarwal and Chu disclose the semiconductor device according to claim 4.
But, fail to disclose wherein a width of the resistor element (324) is 10 nm or more and 40 nm or less; and wherein a width of the resistor element is 10 nm or less.
However,
Jessen discloses in FIG. 4I silicon-silicon carbide-chromium (SiCCr) resistor elements ([0021]) on the order of 10 nm ([0033]), which could be 10 nm or more and 40 nm or less; or 10 nm or less, to produce reduced resistor size for a same resistance as a similar resistor with larger line width (Jessen; [0033]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal and Chu and Jessen as applied to claim 7 above, and further in view of SAKAMOTO et al (US 2015/0130079 A1, hereafter Sakamoto).
Re claim 8, Aggarwal and Chu and Jessen disclose the semiconductor device according to claim 7.
But, fail to disclose wherein each of the upper surface and the lower surface of the resistor element (324) has a plurality of protrusions.
However,
Sakamoto discloses in FIG. 14 wherein each of the upper surface (at 58 α; [0169]) and the lower surface (at 50 α; [0164]) of a conductive element (58; [0160]) has a plurality of protrusions (rough surfaces; [0164] and [0169]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Aggarwal and Chu and Jessen, by using the plurality of protrusions of Sakamoto, such that each of the upper surface and the lower surface of the resistor element (324) has a plurality of protrusions, improving the adhesiveness of the resistor element (Sakamoto; [0177]).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Aggarwal and Chu as applied to claim 4 above, and further in view of Cen et al (US 2021/0351032 A1, hereafter Cen).
Re claims 15-16, Aggarwal and Chu disclose the method according to claim 12.
But, fail to disclose comprising: (a1) after the (a) and before the (b), performing a plasma treatment on an upper surface of the first dielectric film; and (a1) after the (a) and before the (b), cleaning an upper 15 surface of the first dielectric film using SPM, APM or ozonated water.
However,
Cen discloses in FIG. 2 a cleaning method comprising: a H2/Ar plasma, an oxygen plasma, or a water/ozone treatment ([0057]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Aggarwal and Chu, by using the H2/Ar plasma, oxygen plasma, or the water/ozone treatment of Cen, such that (a1) after the (a) and before the (b), to perform a plasma treatment on an upper surface of the first dielectric film; and (a1) after the (a) and before the (b), to clean an upper surface of the first dielectric film using ozonated water, to efficiently clean residues and enhance selectivity of a subsequent deposition process. In some embodiments, an oxygen plasma is used to alleviate selectivity loss issues by cleaning impurities/dangling bonds and terminating a metal and/or dielectric surface as uniform oxide (Cen; [0057]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
The disclosures of US-20220271118-A1 (SiCrC resistor element); US-20210098363-A1 (non-planar resistor element); US-20220081759-A1 (plasma and/or ozone cleaning apparatus); and US-20220102271-A1 (thickness/width/length of resistor elements) aren’t being relied on for producing the claimed resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element contains silicon, chromium, and carbon. The silicon concentration in the resistor element increases from a center part of the resistor element towards an upper surface of the resistor element, and also increases from the center part of the resistor element towards a lower surface of the resistor element.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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