Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Device With Antenna Effect And Plasma Charging Protection Circuit”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12,080,658 B2 to Chen.
Although the claims at issue are not identical, they are not patentably distinct from each other because the Parent Patent renders obvious the Instant Application.
Regarding independent claim 1: Chen teaches (e.g., Claims 1-6) an integrated circuit (IC) device, comprising:
a first die; and a second die coupled to the first die through an input/output (I/O) terminal,
wherein the first die comprises a first antenna effect protection circuit electrically coupled to the I/O terminal,
the first antenna effect protection circuit comprises at least one first transistor of a first type, and at least one second transistor of a second type different from the first type, and
a gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the I/O terminal (Claim 1).
Regarding claim 2: Chen teaches the claim limitation of the IC device of claim 1, on which this claim depends,
wherein the at least one first transistor comprises multiple first transistors, the at least one second transistor comprises multiple second transistors, and in the first antenna effect protection circuit, a number of the first transistors is greater than a number of the second transistors (Claim 2).
Regarding claim 3: Chen teaches the claim limitation of the IC device of claim 2, on which this claim depends,
wherein the first transistors are N-type transistors, and the second transistors are P-type transistors (Claim 3).
Regarding claim 4: Chen teaches the claim limitation of the IC device of claim 2, on which this claim depends,
wherein the first transistors are P-type transistors, and the second transistors are N-type transistors (Claim 4).
Regarding claim 5: Chen teaches the claim limitation of the IC device of claim 1, on which this claim depends,
wherein the second die comprises a second antenna effect protection circuit electrically coupled to the I/O terminal.
Regarding claim 6: Chen teaches the claim limitation of the IC device of claim 5, on which this claim depends,
wherein the second antenna effect protection circuit comprises at least one third transistor of the first type, and at least one fourth transistor of the second type, and a gate terminal, a first terminal and a second terminal of each of the at least one third transistor and the at least one fourth transistor are electrically coupled together, and to the second end of the I/O terminal (Claim 6).
Regarding independent claim 7: Chen teaches (e.g., Claims 7-17) an integrated circuit (IC) device, comprising:
a plurality of active regions extending along a first axis; and
a plurality of gate regions extending along a second axis transverse to the first axis,
wherein the plurality of active regions and the plurality of gate regions are configured as a plurality of transistors, gates, sources and drains of the plurality of transistors are electrically coupled together, and the plurality of active regions is arranged in a doped well region having an H shape (Claim 13).
Regarding claim 8: Chen teaches the claim limitation of the IC device of claim 7, on which this claim depends,
wherein the plurality of active regions is of a same semiconductor type (Claim 13).
Regarding claim 9: Chen teaches the claim limitation of the IC device of claim 7, on which this claim depends,
wherein the H shape of the doped well region comprises: first and second sections extending continuously along the first axis, and spaced from each other along the second axis, and a third section extending continuously along the second axis, and connecting the first and second sections (Claim 10).
Regarding claim 10: Chen teaches the claim limitation of the IC device of claim 9, on which this claim depends,
wherein the plurality of active regions comprises: first through third active regions extending continuously along the first axis, and arranged correspondingly in the first through third sections of the doped well region (Claim 13).
Regarding claim 11: Chen teaches the claim limitation of the IC device of claim 10, on which this claim depends,
wherein the plurality of active regions further comprises: fourth and fifth active regions extending continuously along the first axis, arranged in the first section of the doped well region, and spaced from each other along the second axis (Claim 13).
Regarding claim 12: Chen teaches the claim limitation of the IC device of claim 11, on which this claim depends,
wherein at least one of the fourth active region or the fifth active region overlaps the first active region along the first axis (Claim 11).
Regarding claim 13: Chen teaches the claim limitation of the IC device of claim 12, on which this claim depends,
wherein the plurality of active regions further comprises: sixth and seventh active regions extending continuously along the first axis, arranged in the first section of the doped well region, and spaced from each other along the second axis, at least one of the sixth active region or the seventh active region overlaps the first active region along the first axis, and the first active region is arranged, along the first axis, between the fourth and fifth active regions on one side and the sixth and seventh active regions on another side (Claim 12).
Regarding claim 14: Chen teaches the claim limitation of the IC device of claim 9, on which this claim depends,
wherein the first section of the doped well region has a width along the second axis greater than a width of the second section of the doped well region (Claim 13).
Regarding claim 15: Chen teaches the claim limitation of the IC device of claim 9, on which this claim depends,
wherein the doped well region further comprises: a fourth section extending continuously along the first axis, and spaced from the first section of the doped well region along the second axis, and a fifth section extending continuously along the second axis, and connecting the first and fourth sections of the doped well region, and lengths of the third and fifth sections of the doped well region along the first axis are shorter than lengths of the first, second and fourth sections of the doped well region (Claim 16).
Regarding independent claim 16: Chen teaches (e.g., Claims 7-17) an integrated circuit (IC) device, comprising: a plurality of active regions extending along a first axis; and
a plurality of gate regions extending along a second axis transverse to the first axis, wherein the plurality of active regions and the plurality of gate regions are configured as a plurality of transistors, gates, sources and drains of the plurality of transistors are electrically coupled together, the plurality of active regions comprises first through third active regions of a first semiconductor type, the first active region is spaced from, and overlaps, the second and third active regions along the second axis, the second active region is spaced from, and overlaps, the third active region along the first axis, and the third active region is configured to receive a reference voltage (Claim 9).
Regarding claim 17: Chen teaches the claim limitation of the IC device of claim 16, on which this claim depends,
wherein the plurality of active regions further comprises a fourth active region of a second semiconductor type different from the first semiconductor type, and along the first axis, the fourth active region overlaps at least one of the first active region, the second active region, or the third active region (Claim 15).
Regarding claim 18: Chen teaches the claim limitation of the IC device of claim 17, on which this claim depends,
wherein along the first axis, the fourth active region overlaps all of the first active region, the second active region, and the third active region (Claim 15).
Regarding claim 19: Chen teaches the claim limitation of the IC device of claim 16, on which this claim depends,
wherein the plurality of active regions further comprises fourth and fifth active regions of a second semiconductor type different from the first semiconductor type, along the second axis, the first through third active regions are arranged between the fourth and fifth active regions, and each of the fourth and fifth active regions extends continuously along the first axis and overlaps, along the second axis, the first through third active regions (Claim 16).
Regarding claim 20: Chen teaches the claim limitation of the IC device of claim 19, on which this claim depends,
wherein the plurality of active regions further comprises sixth and seventh active regions of the first semiconductor type, along the second axis, the fourth active region is arranged between the sixth and seventh active regions on one side and the first through third active regions on another side, the sixth and seventh active regions are spaced from each other along the first axis, and the sixth active region is configured to receive the reference voltage (Claim 17).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ouyang et al. (US 2014/0291765 A1).
Regarding independent claim 1: Ouyang teaches (e.g., Figs. 4-5) an integrated circuit (IC) device, comprising:
a first die ([0051] and [0053]: T1); and a second die ([0051] and [0053]: T2) coupled to the first die through an input/output (I/O) terminal ([0050]-[0051]),
wherein the first die comprises a first antenna effect protection circuit ([0053] and [0055]) electrically coupled to the I/O terminal,
the first antenna effect protection circuit comprises at least one first transistor of a first type ([0032] and [0056]: N-MOS), and at least one second transistor of a second type ([0032] and [0056]: PMOS) different from the first type, and
a gate terminal ([0036]-[0037] and [0040]), a first terminal ([0036]-[0039]: source terminal) and a second terminal ([0036]-[0039]: drain terminal) of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the I/O terminal (Figs. 4-5; [0056] and [0058]).
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim but, would be allowable if all rejected independent claims are overcome including the Double Patenting Rejection.
Claims 7-20 would be allowable if the rejections are overcome including the Double Patenting Rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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