DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The information disclosure statement filed July 10, 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention, so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-20 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-18 of US12237229. This is a provisional statutory double patenting rejection since the claims directed to the same invention.
Applicant Claims (18/769,278)
US12237229 B2 Claims
1. A semiconductor structure, comprising: a plurality of fin structures protruding from a substrate and comprising first and second outermost fin structures, wherein top surfaces of the first and second outermost fin structures are aligned on a horizontal plane; and a shallow trench isolation (STI) material on the substrate and surrounding the plurality of fin structures, comprising: a first portion outside the plurality of fin structures, wherein a first height is measured from a first top surface of the first portion to the horizontal plane; and a second portion between the first outermost fin structure and an adjacent inner fin structure, wherein a second height is measured from a second top surface of the second portion to the horizontal plane and the second height is greater than the first height.
1. A semiconductor structure, comprising: a plurality of fins protruding from a substrate and comprising first and second outermost fins and one or more inner fins between the first and second outermost fins, wherein: the first outermost fin comprises first and second sidewalls opposite to each other; the second outermost fin comprises third and fourth sidewalls opposite to each other, wherein the second and third sidewalls face each other; and top surfaces of the first and second outermost fins are aligned on a horizontal plane; and a shallow trench isolation (STI) material on the substrate, comprising: a first portion in contact with the first sidewall and comprising a first top surface, wherein a first height is measured from the first top surface to the horizontal plane; and a second portion between the first outermost fin and an adjacent inner fin of the one or more inner fins and comprising a second top surface, wherein a second height is measured from the second top surface to the horizontal plane and the second height is greater than the first height.
3. The semiconductor structure of claim 1, further comprising one or more inner fin structures protruding from the substrate and between the first and second outermost fin structures.
2. The semiconductor structure of claim 1, wherein the second portion is in contact with inner sidewalls of the first and second outmost fin structures.
2. The semiconductor structure of claim 1, wherein the second portion is in contact with the second and third sidewalls.
4. The semiconductor structure of claim 1, wherein a ratio of the second height over the first height is greater than or equal to about 1 and less than about 1.2.
3. The semiconductor structure of claim 1, wherein a ratio of the second height over the first height is greater than or equal to about 1 and less than about 1.2.
5. The semiconductor structure of claim 1, wherein a difference between the second height and the first height ranges from about 3 nm to about 5 nm.
4. The semiconductor structure of claim 1, wherein a difference between the second height and the first height ranges from about 3 nm to about 5 nm.
6. The semiconductor structure of claim 1, further comprising source/drain terminals and gate structures formed on the plurality of fin structures.
5. The semiconductor structure of claim 1, further comprising source/drain terminals and gate structures formed on the plurality of fins.
7. The semiconductor structure of claim 1, wherein the plurality of fin structures protrude from the first and second top surfaces of the STI material.
6. The semiconductor structure of claim 1, wherein the plurality of fins protrude from the first and second top surfaces of the STI material.
8. The semiconductor structure of claim 1, wherein the STI material comprises silicon oxide.
7. The semiconductor structure of claim 1, wherein the STI material comprises silicon oxide.
9. The semiconductor structure of claim 1, wherein each of the plurality of fin structures comprises a top portion having a substantially uniform width and a bottom portion having a width that gradually changes vertically.
8. The semiconductor structure of claim 1, wherein each of the plurality of fins comprises a top portion having a substantially uniform width and a bottom portion having a width that gradually changes vertically.
10. The semiconductor structure of claim 9, wherein the first and second portions of the STI material are in contact with the bottom portion of the plurality of fin structures.
9. The semiconductor structure of claim 9, wherein the first and second portions of the STI material are in contact with the bottom portion of the plurality of fins.
11. A semiconductor device, comprising: first and second fin structures protruding from a substrate; a shallow trench isolation (STI) material on the substrate, comprising: an inner portion between the first and second fin structures and comprising a first top surface; and an outer portion outside of the first and second fin structures and comprising a second top surface, wherein a first height of the inner portion between the first top surface to a top surface of the first fin structure is equal to or greater than a second height of the outer portion measured between the second top surface and a top surface of the second fin structure; and a gate structure on the STI material and the first and second fin structures.
10. A semiconductor device, comprising: first and second fins protruding from a substrate, wherein top surfaces of the first and second fins are aligned on a horizontal plane; a shallow trench isolation (STI) material on the substrate, comprising: an inner portion between the first and second fins and comprising a first planar top surface, wherein a first height is measured between the first planar top surface and the horizontal plane; and an outer portion outside of the first and second fins and comprising a second planar top surface, wherein a second height is measured between the second planar top surface and the horizontal plane, and wherein the first height is greater than the second height; and a gate structure on the STI material and the first and second fins.
12. The semiconductor structure of claim 11, wherein the gate structure comprises a gate dielectric layer on the first top surface, the second top surface, and the first and second fin structures.
11. The semiconductor device structure of claim 11, wherein the gate structure comprises a gate dielectric layer on the first planar top surface, the second planar top surface, and the first and second fins.
13. The semiconductor structure of claim 11, further comprising one or more fin structures protruding from the substrate and between the first and second fin structures.
12. The semiconductor device structure of claim 11, further comprising one or more fins protruding from the substrate and between the first and second fins, wherein the inner portion of the STI material is between the first fin and a fin of the one or more fins adjacent to the first fin.
14. The semiconductor structure of claim 11, wherein a ratio of the first height over the second height is greater than or equal to about 1 and less than about 1.2.
13. The semiconductor device structure of claim 11, wherein a ratio of the first height over the second height is greater than or equal to about 1 and less than about 1.2.
15. The semiconductor structure of claim 11, wherein each of the first and second fin structures comprises a top portion having a substantially uniform width and a bottom portion having a width that gradually increases towards the substrate.
14. The semiconductor device structure of claim 11, wherein each of the first and second fins comprises a top portion having a substantially uniform width and a bottom portion having a width that gradually changes vertically.
16. The semiconductor structure of claim 15, wherein the inner and outer portions of the STI material are in contact with the bottom portion of first and second fin structures.
15. The semiconductor device structure of claim 15, wherein the inner and outer portions of the STI material are in contact with the bottom portion of first and second fins.
17. A semiconductor device, comprising: first and second fin structures on a substrate and comprising a channel region and a source/drain region; a shallow trench isolation (STI) material on the substrate and comprising a first portion between the first and second fin structures and a second portion outside the first and second fin structures, wherein: the first portion comprises a first top surface; the second portion comprises a second top surface higher than the first top surface; and the channel region and the source/drain region protrude from the first and second top surfaces; and a gate structure on the channel region and the first and second top surfaces.
16. A semiconductor device, comprising: first and second fins on a substrate and comprising a channel region and a source/drain region, wherein top surfaces of the first and second fins are substantially coplanar; a shallow trench isolation (STI) material on the substrate and comprising a first portion between the first and second fins and a second portion outside the first and second fins, wherein: the first portion comprises a first top surface measured a first distance from the top surfaces of the first and second fins; the second portion comprises a second top surface measured a second distance from the top surfaces of the first and second fins; the channel region and the source/drain region protrude from the first and second top surfaces; and the first distance is greater than the second distance; and a common gate structure on the channel region and the first and second top surfaces.
20. The semiconductor structure of claim 17, wherein the first and second top surfaces are planar.
18. The semiconductor structure of claim 17, wherein the first and second fin structures further comprise a lightly doped region between the channel region and the source/drain region.
17. The semiconductor device structure of claim 17, wherein the first and second fins further comprise a lightly doped region between the channel region and the source/drain region.
19. The semiconductor structure of claim 17, further comprising one or more fin structures protruding from the substrate and between the first and second fin structures.
18. The semiconductor device structure of claim 17, further comprising one or more fins protruding from the substrate and between the first and second fins.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8, 11-13, 17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. US 2019/0043857.
Regarding claim 1, Wu et al. in Fig. 2H discloses a semiconductor structure comprising:
A plurality of fin structures (110a-110d) protruding from a substrate (102) and comprising first (110a) and second (110d) outermost fin structures, wherein top surfaces of the first and second outermost fin structures are aligned on a horizontal plane as claimed (see fig. 2H); and a shallow trench isolation (STI) material (see [0025-0026] regarding isolation layer 114 with different materials) on a substrate and surrounding a plurality of fin structures, comprising:
An inner portion (114a & 114e) outside a plurality of fin structures, wherein a first height is measured from the first top surface of the first portion to the horizontal plane as claimed (see top surface 114a between the first height H1 and the substrate 102 in fig. 2H); and a second portion (114b - 114d) between the first outermost fin (110a) and an adjacent inner fin structure (110b), wherein a second height is measured from the second top surface of the second portion to the horizontal plane as claimed (see the top surface 114b between the height H2 and the substrate 102 in fig. 2H) and the second height is greater than the first height (see [0031] & fig. 2H), as noted H2<H1, thereby the height from the top surface 14b to the horizontal plane is higher than the top surface 114a.
Regarding claim 2, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, wherein the second portion (114b-114d) is in contact with the inner sidewalls of the first (110a) and the second outermost (110d) fin structures.
Regarding claim 3, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, wherein one or more inner fin structures (110b-110c) protruding from the substrate and between the first (110a) and the second (110d) outermost fin structures.
Regarding claim 6, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, wherein a source/drain terminals and gate structures form on the plurality of fin structures (see Fig. 1I and [0018, 0046, 0050]).
Regarding claim 7, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, wherein the plurality of fin structures 110 protruding from the first and second top surfaces of the STI material 114.
Regarding claim 8, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, wherein the STI material comprises silicon oxide (see [0025-0026]).
Regarding claim 11, Wu et al. in Fig. 2H discloses a semiconductor device,
comprising:
first 110a and second 110b fins protruding from a substrate 102, wherein
top surfaces of the first and second fins are aligned on a horizontal plane (see fig. 2H); and a shallow trench isolation (STI) material 114 (see [0025-0026]) on a substrate 102, comprising:
an inner portion between the first 110a and second 110b fin structure and comprising a first top surface, wherein a first height H1 is measured between the first top surface to a top surface of the first portion to the horizontal plane as claimed (see top surface 114a between the first height H1 and the substrate 102 in fig. 2H); and
an outer portion between outside of the first 110a and second 110b fin structure and comprising a second top surface, wherein a second height is measured from the second top surface of the second portion to the horizontal plane as claimed (see the top surface 114b between the height H2 and the substrate 102 in fig. 2H) and
wherein the first height H1 is greater than the second height H2; and;
a gate structures (116 & 120) on the STI material and the first and second fin structures as claimed (see Fig 1I and [0046-0052])
Regarding claim 12, Wu et al. discloses the semiconductor structure of claim 11, wherein the gate structure 120 comprises a gate dielectric layer 116 on the first top surface, the second top surface, and the first and second fin structures as claimed (see [0046-0052]).
Regarding claim 13, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 11, wherein one or more fin structures 120 protruding from the substrate and between the first and second fin structures.
Regarding claim 17, Wu et al. in Fig. 2H discloses a semiconductor device,
comprising:
first 110a and second 110b fin structures on a substrate 102 and comprising a channel and a source/drain region as claimed (see Fig. 1I and [0018, 0048, 0050]);
and a shallow trench isolation (STI) material 114 (see [0025-0026]) on a substrate 102, and comprising a first portion between the first 110a and second 11b fin structures and a second portion outside the first 110b and second 110c fin structures, wherein:
the first portion H1 comprising a first top surface; and
the second portion H2 comprise a second top surface is higher than the first top surface; and
the channel region and the source/drain region protruding from the first and second top surfaces as claimed (see Fig. 1I and [0018, 0048, 0050]); and
a gate structure on the channel region and the first and second top surfaces as claimed (see Fig. 1I and [0018, 0048, 0050]).
Regarding claim 19, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 17, wherein one or more fin structures 120 protruding from the substrate and between the first and second fin structures.
Regarding claim 20, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 17, wherein the first and second top surfaces are planar.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not
identically disclosed as set forth in section 102, if the differences between the claimed invention and the
prior arts are such that the claimed invention as a whole would have been obvious before the effective
filing date of the claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2019/0043857 as applied to claims 1 and 11 above, and further in view of the following comments.
Regarding claim 4, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, wherein a ratio of the second height over the first height is greater than or equal to about 1 (see [0031]). However, Wu fails to teach the ratio is less than about 1.2.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d
1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.
1996) (claimed ranges of a result effective variable, which do not overlap the prior art
ranges, are unpatentable unless they produce a new and unexpected result which is
different in kind and not merely in degree from the results of the prior art). See also In re
Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable
in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA
1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to set the ratio is less than about 1.2 as claimed, as an obvious design choice since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Regarding claim 5, the claim is rejected for the same reason as set forth above in claim 1. However, Wu fails to teach a difference between the second height and the first height ranges from about 3 nm to about 5 nm. Since Wu does teach a difference between the second height and the first height ranges from about 0.1 nm to about 2 nm (see [0031]).
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d
1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.
1996) (claimed ranges of a result effective variable, which do not overlap the prior art
ranges, are unpatentable unless they produce a new and unexpected result which is
different in kind and not merely in degree from the results of the prior art). See also In re
Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable
in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA
1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to set the ranges from about 3 nm to about 5 nm as claimed, as an obvious design choice since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Regarding claim 14, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 11, wherein a ratio of the second height over the first height is greater than or equal to about 1 (see [0031]). However, Wu fails to teach the ratio is less than about 1.2.
Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d
1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.
1996) (claimed ranges of a result effective variable, which do not overlap the prior art
ranges, are unpatentable unless they produce a new and unexpected result which is
different in kind and not merely in degree from the results of the prior art). See also In re
Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable
in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA
1955) (selection of optimum ranges within prior art general conditions is obvious).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to set the ratio is less than about 1.2 as claimed, as an obvious design choice since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Claim(s) 9-10 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2019/0043857 as applied to claims 1 and 11 above, and further in view of Xu et al. US 10361125B2.
Regarding claim 9, Wu et al. in Fig. 2H discloses the semiconductor structure of claim 1, Wu et al. does not expressly disclose wherein each of the plurality of fins comprises a top portion having a substantially uniform width and a bottom portion having a width that gradually changes vertically.
Xu et al. in Fig. 10 shows a plurality of fins 151 comprises a top portion having
a substantially uniform width and a bottom portion having a width that gradually changes vertically.
Therefore, it would have been obvious to one having ordinary skill in the art
before the effective filing date of the claimed invention to incorporate the teachings of
Xu et al. in the semiconductor structure of Wu et al. for the purpose of having a
known fin structure with a top portion having a substantially uniform width and a bottom
portion having a width that gradually changes vertically, as the court has held that
choosing from a finite number of identified, predictable solutions, with a reasonable
expectation of success is prima facie obvious. KSR Int'! Co. v. Teleflex Inc., 550 U.S.
398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Regarding claim 10, Wu et al. in view of Xu et al. teaches the semiconductor structure of claim 9, wherein the first and second portions of the STI material are in contact with the bottom portion of the plurality of fin structures as claimed (see Wu, Fig. 2H and Xu, Fig. 10).
Regarding claim 15, the claim is rejected for the same reason as set forth above in claim 9.
Regarding claim 16, Wu et al. in view of Xu et al. teaches the semiconductor
structure of claim 15. Xu et al. would teach wherein the inner and outer portions
of the STI material are in contact with the bottom portion of first and second fin structures as claimed (see Wu, Fig 2H and Xu, Fig 8).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2019/0043857 as applied to claim 17 above, and further in view of Hung et al. US 2019/0097026.
Regarding claim 18, Wu et al. in Fig. 2H discloses the semiconductor structure
of claim 17. Wu et al. does not expressly disclose wherein the first and second fin structures further comprise a lightly doped region between the channel region and the source/drain region. Hung et al. discloses a lightly doped region within the substrate (see [0011]) for minimizing hot carrier effects.
Therefore, it would have been obvious to one having ordinary skill in the art
before the effective filing date of the claimed invention to incorporate the teachings of
Hung et al. in the semiconductor structure of Wu et al. for the purpose of minimizing hot
carrier effects.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to THU VAN NGUYEN whose telephone number is
(571)270-7396. The examiner can normally be reached M-F, 9-5 pm (CST).
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the organization where this application or proceeding is assigned is 571-273-8300.
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/THU VAN NGUYEN/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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