Prosecution Insights
Last updated: August 14, 2026
Application No. 18/769,637

METHOD AND SYSTEM OF PERFORMING COLLECTIVE DIE-TO-WAFER BONDING

Non-Final OA §102§103
Filed
Jul 11, 2024
Priority
Jul 11, 2023 — EU 23184798.9
Examiner
FERNANDES, ERROL V
Art Unit
Tech Center
Assignee
Ihp Gmbh-Innovations For High Performance Microelectronics/Leibniz-Instit Für Innovative Mikroelekt
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
694 granted / 814 resolved
+25.3% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
16 currently pending
Career history
826
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
33.0%
-7.0% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 814 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4, 7-10 and 14-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. US 2022/0190193 A1. Regarding claims 1, 4 and 7-10, Hong discloses: A method of performing collective die-to-wafer bonding (Figs. 2, 4 and 5), the method comprising the steps of: - providing a carrier wafer (110/120) having a back side (bottom) and a bonding side (top) opposite the back side and comprising on the bonding side one or more pockets (between 120s) that each are configured for accommodating a die, respectively (Fig. 2C), - providing a target substrate (410) comprising an integrated circuit (414 driving layer), hereinafter target IC, and one or more target bonding pads (para 0077; electrode patterns formed on target substrate 410) for connecting the one or more dies to the target IC (Fig. 5A), - placing one or more dies (130) in the one or more pockets, respectively (Fig. 4A), and - bonding the one or more dies placed in the one or more pockets to the target substrate by bringing the one or more dies into contact with the one or more target bonding pads (Fig. 5B). (claim 4) Fig. 4B. (claim 7) Figs. 4A/4B. (claim 8) Figs. 4A/4B. (claim 9) para 0079. (claim 10) Fig. 5C. Regarding claim 14, Hong discloses: A target substrate (410) comprising an integrated circuit (414 driving layer) (Figs. 5A/5B), hereinafter target IC, with target bonding pads (para 0077; electrode patterns formed on target substrate 410) and one or more dies (130) each die comprising a die bonding pad (130s shown with die pads on top side), wherein the dies are connected to the target bonding pads via the die bonding pads, respectively (Fig. 5B). Regarding claims 15-17, Hong discloses: A system for collective die-to-wafer bonding (Figs. 2, 4 and 5), the system comprising: - a carrier wafer providing unit configured for providing a wafer carrier (110/120) having a back side (bottom) and an opposite bonding side (top) and comprising on the bonding side one or more pockets (between 120s) that each are configured for accommodating a die (Fig. 2C), - a target substrate providing unit configured for providing a target substrate (410) comprising an integrated circuit (414 driving layer), hereinafter target IC, and one or more target bonding pads (para 0077; electrode patterns formed on target substrate 410) for connecting the one or more dies to the target IC (Fig. 5A), - a die placement unit configured for placing one or more dies (130) in the one or more pockets, respectively (Fig. 4A), and - a die bonding unit configured for bonding the one or more dies placed in the one or more pockets to the target substrate by bringing the one or more dies in contact with the one or more target bonding pads (Fig. 5B). (claim 16) paras 0077-0078. (claim 17) Figs. 5A-5C; paras 0077-0080. Claim(s) 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by England et al. US 10,818,570 B1. Regarding claim 13, England discloses: A carrier wafer comprising a first wafer (Fig. 3; 300) with one or more exposed pockets (306) that are each configured for accommodating a respective die (200), the first wafer forming a bonding side of the carrier wafer, and a second wafer (Fig. 4; 400) bonded to the first wafer, the second wafer forming a backside of the carrier wafer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5, 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. US 2022/0190193 A1. Regarding claim 5, although Hong does not specifically disclose “wherein a given pocket of the one or more pockets, seen in a top view, defines an opening that is no more than 1 um larger in each lateral direction than a surface area of a cross-section of a die of the one or more dies that is to be placed in that pocket”, Hong does depict sufficient space for the die 130 to be placed within the pocket. As a result, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the pocket opening having spacing no more than 1 um in each lateral direction in order to accommodate the die since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claims 11 and 12, although Hong does not specifically disclose “(claim 11) wherein the one or more pockets have at least one inclined side wall”; and “(claim 12) wherein an area of an opening at the bonding side of at least one pocket of the one or more pockets is larger than an area of a bottom of the at least one pocket”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine inclined sidewalls of Hong’s flexible rib structure 120 to further ease the transfer of die into the openings during the process discussed in Figs. 3A-3C. Furthermore, it has been held that the provision of adjustability, where needed, involves only routine skill in the art. In re Stevens, 101 USPQ 284 (CCPA 1954). Claims 2, 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong, as applied to claim 1 above, in view of England et al. US 10,818,570 B1. Regarding claim 2 and 3, Hong does not disclose: (claim 2) wherein providing the carrier wafer comprises etching the one or more pockets into a first wafer and bonding the first wafer to a second wafer to obtain the carrier wafer, wherein the first wafer comprising the one or more pockets forms the bonding side of the carrier wafer; and (claim 3) wherein the bonded first wafer is ground until the one or more etched pockets are exposed to form the bonding side of the carrier wafer. England discloses a patent from a similar field of endeavor in which: (claim 2) wherein providing the carrier wafer comprises etching the one or more pockets (306) into a first wafer (Fig. 3; 300, col 4 lines 4-15) and bonding the first wafer to a second wafer (Fig. 4; 400) to obtain the carrier wafer, wherein the first wafer comprising the one or more pockets forms the bonding side of the carrier wafer (Fig. 5B); and (claim 3) wherein the bonded first wafer is ground until the one or more etched pockets are exposed to form the bonding side of the carrier wafer (Fig. 5D; col 5 lines 28-43; backgrinding). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the similar carrier structure of Hong using the process described by England since such processes are standard in determining the carrier wafers with window openings. Regarding claim 6, Hong does not disclose: wherein placing the one or more dies in the one or more pockets comprises aligning the one or more dies relative to the one or more pockets, wherein, preferably, the alignment of the one or more dies is performed with reference to an alignment feature, preferably, one or more side walls of the pocket, inherent to the one or more corresponding pockets, respectively, or with reference to one or more alignment marks present on the carrier wafer and having a known spatial relationship relative to the one or more pockets, respectively. England discloses a patent from a similar field of endeavor in which: wherein placing the one or more dies in the one or more pockets comprises aligning the one or more dies relative to the one or more pockets, wherein, preferably, the alignment of the one or more dies is performed with reference to an alignment feature, preferably, one or more side walls of the pocket, inherent to the one or more corresponding pockets, respectively, or with reference to one or more alignment marks present on the carrier wafer and having a known spatial relationship relative to the one or more pockets, respectively (Fig. 5B; col 5 lines 4-19 alignment marks fabricated on the window spacers 308). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the alignment strategy of England to assist in placing the die within the openings in the carrier wafer thereby achieving a finer, accurate placement of the die. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Jul 11, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.9%)
2y 2m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 814 resolved cases by this examiner. Grant probability derived from career allowance rate.

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