Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 11 and 19.
b. Claims 1-20 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 03/12/2025. The changes and remarks disclosed therein were considered.
The specification has been amendment. Claims 1-20 are pending in the application.
Drawings
3. The drawings were received on 07/11/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/28/2025. The information disclosed therein was considered.
Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/07/2025. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-3, 5, 9-11 and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jung et al (Patent No.: US 11,270,762 B1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2) comprising:
a memory array including a plurality of memory cells (a memory array includes a plurality of bitcell 105, Fig. 1), wherein each of the plurality of memory cells is accessible through a plurality of bit lines (a plurality of bit lines bl, blb, Fig. 1);
a comparator (an address comparator 101, Fig. 1) configured to receive a first address signal indicating a first row along which a first one of the memory cells (the bitcell 105) is disposed and a second address signal indicating a second row along which a second one of the memory cells is disposed (the bitcell 105 form the first column and the corresponding bitcell in the second column form a bitcell group that share a common address that identifies word line wl and the group of multiplexer columns), and generate a control signal (a clock signal CLK 102, Fig. 1) with a logic state indicating whether the first row is identical to the second row (the clock signal CLK coupled to the self-timed circuit 155, which are generate the output rm and cts_pre_n to the memory bitcell 105, Fig. 1);
a timing circuit (a self-timed circuit 155, Fig. 1) configured to skip pre-charging (a bitline pre-charge circuit 150, Fig. 1) the bit lines of the second memory cell after accessing the first memory cell, based on the logic state of the control signal (the self-timed circuit 155 such as triggered by memory clock signal 102 and modified from such conventional function to accommodate the burst mode 145 (burst_n) signal such as an active low burst mode signal so that word line is not sserted, the bitline are not pre-charged, and the charge transfer transistors are not switched on during a burst mode operation, see at least in Figures 1-2, column 6, lines 15 to column 9, lines 26 and the related disclosures).
Regarding dependent claim 2, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2), wherein the first memory cell (the bitcell 105) is first accessed based on asserting a first clock pulse, and the second memory cell (the bitcell 105) is then accessed based on asserting a second clock pulse (the bitcell 105 for the first column and the corresponding bitcell in the second column from a bitcell group that share a common address that identifies word line wl and the group of multiplexed columns, Fig. 1).
Regarding dependent claim 3, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2), wherein the first clock pulse and the second clock pulse are within one clock cycle (the bitcell 105 regardless of whether a read operation occurs with or without the burst mode, each read operation is responsive to a cycle of a memory clock signal 102, Fig. 1, column 6, lines 46-49).
Regarding dependent claim 5, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2), wherein the comparator (address comparator 101 and 300, Figs 1 and 3) includes a plurality of XOR gates (XOR gate 320, Fig. 3) each with 2 inputs, one inverter (an inverter 340, Fig. 3), and a plurality of n-type transistors (a transistor NMOS M5, M6).
Regarding dependent claim 9, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2) further comprising a latch (a Dout Latch circuit 140, Fig. 3) operatively coupled between the comparator (the address comparator 101) and the timing circuit (the Self-timed circuit 155).
Regarding dependent claim 10, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2), wherein each of the memory cells includes a six-transistor static random access memory (SRAM) cell (a sram circuit 100, Figures 1 and 2).
Regarding to independent claim 11, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2) comprising:
a memory array including a plurality of memory cells (a memory array includes a plurality of bitcell 105, Fig. 1), wherein each of the plurality of memory cells is accessible through a plurality of bit lines (a plurality of bit lines bl, blb, Fig. 1);
a comparator (an address comparator 101, Fig. 1) configured to compare a first address signal with a second address signal so as to generate a control signal (a clock signal 102 CLK), wherein the first address signal, in part, indicates a first row of a first memory cell and the second address signal, in part, indicates a second row of a second memory cell (the bitcell 105 form the first column and the corresponding bitcell in the second column form a bitcell group that share a common address that identifies word line wl and the group of multiplexer columns), and wherein the control signal (the clock signal 102) has a logic state indicating whether the first row is identical to the second row (the clock signal 102 CLK coupled to the self-timed circuit 155, which are generate the output rm and cts_pre_n to the memory bitcell 105, Fig. 1); and
a timing circuit (a self-timed circuit 155, Fig. 1) configured to skip pre-charging bit lines of the second memory cell after accessing the first memory cell, based on the logic state of the control signal (the self-timed circuit 155 such as triggered by memory clock signal 102 and modified from such conventional function to accommodate the burst mode 145 (burst_n) signal such as an active low burst mode signal so that word line is not sserted, the bitline are not pre-charged, and the charge transfer transistors are not switched on during a burst mode operation, see at least in Figures 1-2, column 6, lines 15 to column 9, lines 26 and the related disclosures).
Regarding dependent claim 16, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2), wherein the comparator (address comparator 101 and 300, Figs 1 and 3) includes a plurality of XOR gates (XOR gate 320, Fig. 3) each with 2 inputs, one inverter (an inverter 340, Fig. 3), and a plurality of n-type transistors (a transistor NMOS M5, M6).
Regarding dependent claim 17, Jung et al in Figures 1-6 are directly discloses a memory circuit (a sram memory circuits 100 and 200, Figures 1-2) further comprising a latch (a Dout Latch circuit 140, Fig. 3) operatively coupled between the comparator (the address comparator 101) and the timing circuit (the Self-timed circuit 155).
Allowable Subject Matter
6. Claims 4, 6-8, 12-15 and 18, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 4, the prior art fails to tech or suggest the claimed limitations, namely the comparator includes a plurality of first XNOR gates each with 2 inputs, a plurality of NAND gates each with 3 inputs, and a second NOR gate with 3 inputs.
With respected to dependent claims 6-8, the prior art fails to tech or suggest the claimed limitations, namely the timing circuit includes a first NAND gate and a second NAND gate, wherein the first NAND gate is configured to receive the control signal and a phase signal so as to provide an output, and the second NAND gate is configured to receive the output and a logically inverted clock pulse so as to provide a pre-charge signal configured for pre-charging the bit lines of the memory array.
With respected to dependent claims 12-14, the prior art fails to tech or suggest the claimed limitations, namely, during a first cycle of a clock signal in which the first and second memory cells are sequentially accessed, the timing circuit is configured to: before accessing the first memory cell, generate a pre-charge signal with a first logic state to pre-charge bit lines of the first memory cell before accessing the first memory cell; after accessing the first memory cell, generate the pre-charge signal with a second logic state to skip pre-charging the bit lines of the second memory cell, responsive to receiving the logic state of the control signal indicating that the first row is identical to the second row.
With respected to dependent claim 15, the prior art fails to tech or suggest the claimed limitations, namely the comparator includes a plurality of first XNOR gates each with 2 inputs, a plurality of NAND gates each with 3 inputs, and a second NOR gate with 3 inputs.
With respected to dependent claim 18, the prior art fails to tech or suggest the claimed limitations, namely the timing circuit includes a first NAND gate configured to receive the control signal and provide an output, and a second NAND gate configured to receive the output and provide a pre-charge signal.
7. Claims 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 19: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “generating a pre-charge signal with a logic state to cease pre-charging the bit lines of the first memory cell; accessing the first memory cell for read or write operation, responsive to a first clock pulse of a clock signal being asserted; skipping pre-charging bit lines of the second memory cell, responsive to identifying the logic state of the control signal; and accessing the second memory cell for read or write operation, responsive to a second clock pulse of the clock signal being asserted” in a method for operating a memory circuit as claimed in the independent claim 19. Claim 20 is also allowed because of their dependency on claim 19.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al (US. 2017/0110169 A1) discloses memory device and system supporting command bus training and operating method thereof.
Park et al (US. 11,461,176 B2) discloses memory device and memory system.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov