DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species B in the reply filed on April 15, 2026 is acknowledged. Accordingly, claims 1-7 have been withdrawn from further consideration, and claims 8-13 have been examined as follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
There is insufficient antecedent basis for the following limitations in the claims:
Claim 10, last line – “the first semiconductor layer”
Claim 12, lines 7 and 9 – “the first connection line” and “the second connection line”
Claim 11 is also rejected by virtue of its dependence on claim 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0083309) in view of Lee et al. (US 2019/0081090), each of record in IDS.
Regarding claim 8, Wang discloses a display panel (Figs. 1-14) comprising:
a substrate (110) including a display area (DA) and a peripheral area (PA) surrounding the display area (Fig. 1);
a plurality of pixel circuits (PX) each arranged in an area where a row intersects a column in the display area of the substrate (Figs. 1, 7-9, 11, 13), and including a silicon-based thin-film transistor (M1, T1) and an oxide-based thin-film transistor (M2, T3-T7) (paras. [0064, 0110]);
a plurality of voltage lines (VL, 141, 161) connected to the silicon-based thin-film transistor (M1, T1) of each of the plurality of pixel circuits (PX) (Figs. 7-14; paras. [0109, 0113, 0128]); and
a shield layer (120) arranged between the substrate (110) and the silicon-based thin-film transistors (M1, T1) of the plurality of pixel circuits (PX) (Figs. 2-6, 10, 12, 14), and a voltage (ELVDD) which is a same as a voltage applied to the plurality of voltage lines (VL, 141, 161) being applied to the shield layer (120) (Figs. 7-14; paras. [0113, 0140]), the shield layer including:
a plurality of patterns (120) overlapping the silicon-based thin-film transistor (M1, T1) of each of the plurality of pixel circuits (PX) (Figs. 2-6, 9-14); and
first connection lines (161) connecting the plurality of patterns (120) arranged in a column direction, extending in the column direction, and arranged on a two-column basis (Figs. 9, 11, 13; paras. [0056, 0132]).
Wang fails to explicitly disclose second connection lines connecting the plurality of patterns arranged in a row direction, extending in the row direction, and arranged on a row basis.
However, Lee discloses a display panel (Figs. 1-13), the shield layer (140) including second connection lines (140B2) connecting the plurality of patterns (140A) arranged in a row direction, extending in the row direction, and arranged on a row basis (Figs. 6, 8, 11, 13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate second connection lines connecting the plurality of patterns arranged in a row direction, extending in the row direction, and arranged on a row basis, as in Lee, into the display panel of Wang to form a lattice shielding pattern for maximum connectivity.
Regarding claim 9, Wang discloses wherein the shield layer (120) includes a metal material (para. [0071]).
Regarding claim 10, Wang discloses further comprising:
a first inorganic layer (10; para. [0138]) between the substrate (110) and the shield layer (120) (Figs. 2-6, 10, 12, 14); and
a second inorganic layer (11; para. [0143]) between the shield layer (120) and the first semiconductor layer (21, A1) (Figs. 2-6, 10, 12, 14).
Regarding claim 11, Wang discloses wherein the substrate (110) includes an organic layer (para. [0137]).
Regarding claim 12, Wang discloses wherein the silicon-based thin-film transistor (M1, T1) of each of the plurality of pixel circuits (PX) includes a semiconductor layer (21, A1) and a gate electrode (22, 43, G1) overlapping a portion of the semiconductor layer (Figs. 2-6, 10, 12, 14), and
the display panel further includes:
a first signal line (SL, 131) and a second signal line (VL, 133, 151) each, in a plan view, adjacent to the semiconductor layer (21, A1) with the semiconductor layer therebetween, extending in the row direction, and including a portion overlapping the first connection line (161) (Figs. 8, 9, 11, 13; paras. [0132]); and
a third signal line (DL, 171) adjacent to the semiconductor layer (21, A1), extending in the column direction (Figs. 7-8; para. [0129]).
Wang fails to explicitly disclose the third signal line including a portion overlapping the second connection line.
However, Lee discloses the third signal line (171) including a portion overlapping the second connection line (140B2) (Figs. 3, 6, 8, 11, 13).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the third signal line including a portion overlapping the second connection line, as in Lee, into the display panel of Wang to expectedly cross paths upon forming a lattice shielding pattern.
Regarding claim 13, Wang discloses further comprising a voltage supply line (VL, 141) arranged in the peripheral area (PA) and connected to the shield layer (120) (paras. [0055, 0140]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAISLEY L WILSON whose telephone number is (571)270-5023. The examiner can normally be reached Monday-Friday, 9:00am-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MICHAEL CALEY can be reached at 571-272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAISLEY L WILSON/Primary Examiner, Art Unit 2871
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