DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-11 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US 2022/0238571 A1; hereafter Park).
Regarding claim 1, Park teaches an image sensor (see e.g., image sensor, Figures 3-5 and 8-9), comprising:
a substrate including a plurality of pixel regions including a first pixel region and a second pixel region adjacent to each other (see e.g., first substrate 1 includes a pixel array region APS which includes a plurality of unit pixels UP adjacent to each, Para [0044], Figure 4);
a photoelectric converter at the substrate; and (see e.g., photoelectric conversion portion PD disposed in the first substrate 1, Para [0046], Figure 4)
a pixel isolation portion that separates the first pixel region and the second pixel region based on penetrating at least a part of the substrate between the first pixel region and the second pixel region (see e.g., pixel isolation portion DTI disposed in the first substrate 1 to isolate and /or define the unit pixels UP in the pixel array region APS, Para [0045], Figure 4),
wherein the pixel isolation portion includes first and second insulation portions respectively adjacent to the first and second pixel regions (see e.g., insulating liner 12 includes first and second portions respectively adjacent to the first and second unit pixels UP, Para [0058], Figure 4), and a conductive layer and an inner layer between the first and second insulation portions (see e.g., conductive structure 20, includes a first conductive pattern 14a, a second conductive pattern 14b and a connection conductive pattern 18, and first filling insulation pattern 16 between the first and second portions of the insulating liner 12, Paras (0052], [0053], Figure 4),
wherein the conductive layer and the inner layer include different materials, and (see e.g., first conductive pattern 14a, second conductive pattern 14b and connection conductive pattern 18 may include doped polysilicon, the first filling insulation pattern 16 may include silicon oxide, Paras [0055], [0058], Figure 4)
wherein the pixel isolation portion includes
PNG
media_image1.png
620
774
media_image1.png
Greyscale
Modified Figure 3, Park
a first portion including a portion where the conductive layer occupies a space defined between the first and second insulation portions in an intersection direction that intersects an extension direction of the pixel isolation portion, and (see e.g., as shown in modified Figure 3, upper or lower portion of the pixel isolation portion DTI between adjacent pixels is the first portion which includes first conductive pattern 14a, second conductive pattern 14b and first filling insulation pattern 16 between the first and second portions of the insulating liner 12 in an extension direction that intersects an extension direction of the pixel isolation portion DTI, Para [0053], Figure 4)
a second portion including the conductive layer and the inner layer between the first and second insulation portions in the intersection direction (see e.g., as shown in modified Figure 3, middle portion of the pixel isolation portion DTI between adjacent pixels includes the first conductive pattern 14a, second conductive pattern 14b and first filling insulation pattern 16 between the first and second portions of the insulating liner 12 in the intersection direction, Paras [0052], [0053], Figure 4).
Regarding claim 2, Park, as referred in claim 1, further teaches
wherein:
the inner layer has a refractive index less than a refractive index of the conductive layer, and (see e.g., the first and second conductive patterns 14a and 14b and connection conductive pattern 18 comprise doped polysilicon and the first filling insulation pattern 16 comprises silicon oxide. The refractive index of silicon oxide (presence of air gap further reduces the refractive index) is less than the refractive index of doped polysilicon conductive layer, Paras [0055], [0058], Figure 4).
the inner layer includes an inner insulation layer including at least one of
an insulating material, or
inner surfaces at least partially defining a space portion that has an internal space between opposing surfaces of the conductive layer in the intersection direction (see e.g., first filling insulation pattern 16 includes an air gap region AG in the pixel isolation portion DTI between the first conductive pattern 14a and the second conductive pattern 14b in the intersection direction, Para [0060], Figure 4).
Regarding claim 3, Park, as referred in claim 1, further teaches
wherein:
in the second portion, the conductive layer includes first and second conductive portions respectively on the first and second insulation portions, and the inner layer is between the first conductive portion and the second conductive portion in the intersection direction (see e.g., as shown in modified Figure 3, second portion of the pixel isolation portion DTI between adjacent pixels includes first conductive pattern 14a and the second conductive pattern 14b on the first and second portions of the insulating liner 12 and the first filling insulation pattern 16 is between first conductive pattern 14a and the second conductive pattern 14b, Figure 4).
Regarding claim 4, Park, as referred in claim 3, further teaches
wherein:
in the second portion, the inner layer includes first and second inner insulation portions respectively on the first and second conductive portions, and one or more inner surfaces at least partially defining a space portion between the first and second inner insulation portions in the intersection direction (see e.g., as shown in modified Figure 3, second portion of the pixel isolation portion DTI between adjacent pixels includes first conductive pattern 14a and the second conductive pattern 14b on the first and second portions of the insulating liner 12 and the first filling insulation pattern 16 is between first conductive pattern 14a and the second conductive pattern 14b. The first filling insulation pattern includes an air gap AG, Figure 4).
Regarding claim 5, Park, as referred in claim 4, further teaches
wherein:
in the second portion, the inner layer includes an end insulation portion at least partially defining one end of the space portion (see e.g., second portion of the pixel isolation portion DTI between adjacent pixels, as shown in modified Figure 3, includes a protrusion 24p, including for example aluminum oxide or hafnium oxide, is formed over one end of the air gap region AG, Para [0065], Figure 4).
Regarding claim 6, Park, as referred in claim 3, further teaches
wherein:
in the second portion, the inner layer includes first and second inner insulation portions respectively on the first and second conductive portions, and an additional inner insulation layer between the first and second inner insulation portions (see e.g., as shown in modified Figure 3, second portion of the pixel isolation portion DTI between adjacent pixels includes first conductive pattern 14a and the second conductive pattern 14b on the first and second portions of the insulating liner 12 and the first filling insulation pattern 16 is between first conductive pattern 14a and the second conductive pattern 14b. The first filling insulation pattern includes an air gap AG which may be filled with fixed charge layer protrusion 24p, Para [0089], Figures 4 and 8-9).
Regarding claim 7, Park, as referred in claim 3, further teaches
wherein:
in the second portion, the inner layer includes a filling insulation portion that occupies a space defined between the first and second conductive portions in the intersection direction (see e.g., as shown in modified Figure 3, second portion of the pixel isolation portion DTI between adjacent pixels includes first conductive pattern 14a and the second conductive pattern 14b on the first and second portions of the insulating liner 12 and the first filling insulation pattern 16 is between first conductive pattern 14a and the second conductive pattern 14b. The first filling insulation pattern includes an air gap AG which maybe filled with fixed charge layer protrusion 24p, Para [0089], Figures 8-9).
Regarding claim 8, Park, as referred in claim 3, further teaches
wherein:
a thickness of the first conductive portion or the second conductive portion is less than a thickness of the first insulation portion or the second insulation portion, or
the thickness of the first conductive portion or the second conductive portion is less than a thickness of the inner layer (see e.g., as seen from Figure 5A the thickness of either the first conductive pattern 14a or the second conductive pattern 14b is less than the thickness of the first filling insulation pattern 16 plus the air gap region AG).
Regarding claim 10, Park, as referred in claim 1, further teaches
when viewed in a plan view, a total length of the second portion is longer than a total length of the first portion, or
when viewed in a plan view, a ratio of the total length of the second portion to a length of the pixel isolation portion is greater than 50% (see e.g., as shown in modified Figure 3, the second portion of the pixel isolation portion DTI between adjacent pixels has a length longer than the first portion of the DTI).
Regarding claim 11, Park, as referred in claim 1, further teaches
wherein:
when viewed in a plan view, the first portion is at an edge portion or a central portion of the pixel isolation portion (see e.g., as shown in modified Figure 3, the first portion of the pixel isolation portion DTI between adjacent pixels is at the edge of the DTI).
Regarding claim 14, Park, as referred in claim 1, further teaches
wherein:
the conductive layer includes a polycrystalline semiconductor including a dopant, and (see e.g., the first and second conductive patterns 14a and 14b and connection conductive pattern 18 comprise doped polysilicon, Para [0055], Figure 4)
the inner layer includes at least one of oxide, nitride, oxynitride, fluoride, or one or more inner surfaces defining a space portion having an internal space (see e.g., the first filling insulation pattern 16 comprises silicon oxide and may also have an air gap, Para [0058], Figure 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0238571 A1; hereafter Park) in view of Lee et al. (US 2016/0099267 A1; hereafter Lee).
Regarding claim 9, Park, as referred in claim 1, does not explicitly teach
“a width of the second portion is larger than a width of the first portion”.
In a similar field of endeavor Lee teaches
a width of the second portion is larger than a width of the first portion (see e.g., the widths L11 and L14 of the DTI at the centers of the sides of the active regions 120a-1, 120a-2, 120a-3, and 120a-4 are greater than the widths L12, L13, L15, and L16 of the DTI at the side ends of the active regions 120a-1, 120a-2, 120a-3, and 120a-4, Para [0049], Figure 7)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of a width of the second portion is larger than a width of the first portion in the device of Park the size of a dead zone that does not receive light is reduced, as a result, a fill factor indicating light receiving performance is increased.
Regarding claim 15, Park teaches an image sensor (see e.g., image sensor, Figures 3-5 and 8-9), comprising:
a substrate including a plurality of pixel regions (see e.g., first substrate 1 includes a pixel array region APS which includes a plurality of unit pixels UP adjacent to each, Para [0044], Figure 4);
a photoelectric converter at the substrate (see e.g., photoelectric conversion portion PD disposed in the first substrate 1, Para [0046], Figure 4);
a light scattering pattern at a position adjacent to one surface of the substrate; and (see e.g., first fixed charge layer 24 and a second fixed charge layer 42 made of metal oxide or fluoride including at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), or a lanthanoid adjacent to one surface of the substrate 1, Paras [0065], [0066], Figure 4)
a pixel isolation portion that separates the plurality of pixel regions based on penetrating at least a part of the substrate between the plurality of pixel regions (see e.g., pixel isolation portion DTI disposed in the first substrate 1 to isolate and /or define the unit pixels UP in the pixel array region APS, Para [0045], Figure 4),
wherein the pixel isolation portion includes a first portion and a second portion, ….in an intersection direction that intersects an extension direction of the pixel isolation portion, and (see e.g., as shown in modified Figure 3, upper or lower portion of the pixel isolation portion DTI between adjacent pixels is the first portion and the middle portion of the pixel isolation portion DTI between adjacent pixels is the second portion, Para [0053], Figure 4)
wherein the second portion includes an insulation layer adjacent to the plurality of pixel regions, a conductive layer on the insulation layer, and an inner layer at an inside of the conductive layer(see e.g., the second portion of the pixel isolation portion DTI includes the first conductive pattern 14a, second conductive pattern 14b and first filling insulation pattern 16 between the first and second portions of the insulating liner 12 in the intersection direction, Paras [0052], [0053], Figure 4), the inner layer having a refractive index less than a refractive index of the conductive layer (see e.g., the first and second conductive patterns 14a and 14b and connection conductive pattern 18 comprise doped polysilicon and the first filling insulation pattern 16 comprises silicon oxide. The refractive index of silicon oxide (presence of air gap further reduces the refractive index) is less than the refractive index of doped polysilicon conductive layer, Paras [0055], [0058], Figure 4).
Park does not explicitly teach
“the second portion having a width greater than a width of the first portion”
In a similar field of endeavor Lee teaches
the second portion having a width greater than a width of the first portion (see e.g., the widths L11 and L14 of the DTI at the centers of the sides of the active regions 120a-1, 120a-2, 120a-3, and 120a-4 are greater than the widths L12, L13, L15, and L16 of the DTI at the side ends of the active regions 120a-1, 120a-2, 120a-3, and 120a-4, Para [0049], Figure 7)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lee’s teachings of the second portion having a width greater than a width of the first portion in the device of Park the size of a dead zone that does not receive light is reduced, as a result, a fill factor indicating light receiving performance is increased.
Regarding claim 16, Park, as modified by Lee, teaches the limitations of claim 15 as mentioned above. Park
wherein:
the plurality of pixel regions includes a first pixel region and a second pixel region adjacent to each other in one direction (see e.g., pixels regions PX adjacent to each other along x and y directions, Figure 3), and the pixel isolation portion extends in a direction intersecting the one direction between the first pixel region and the second pixel region (see e.g., the pixel isolation portion DTI extends between adjacent pixels regions PX, Figure 3),
the insulation layer includes first and second insulation portions respectively adjacent to the first and second pixel regions (see e.g., insulating liner 12 includes first and second portions respectively adjacent to the first and second unit pixels UP, Para [0058], Figure 4),
the first portion has an electrical connection structure between the first and second insulation portions at least partially defined by the conductive layer, and (see e.g., the first portion of the pixel isolation portion DTI includes conductive structure 20, with a first conductive pattern 14a, a second conductive pattern 14b and a connection conductive pattern 18, and first filling insulation pattern 16 between the first and second portions of the insulating liner 12, Paras (0052], [0053], Figure 4)
the second portion has a total reflection structure at least partially defined by the conductive layer and the inner layer (see e.g., the second portion of the pixel isolation portion DTI includes conductive structure 20, with a first conductive pattern 14a, a second conductive pattern 14b and a connection conductive pattern 18, and first filling insulation pattern 16 between the first and second portions of the insulating liner 12, Paras (0052], [0053], Figure 4.
Regarding claim 17, Park, as modified by Lee, teaches the limitations of claim 15 as mentioned above. Park
wherein:
the inner layer includes an inner insulation layer including at least one of
an insulating material, or
inner surfaces at least partially defining a space portion having an internal space between opposing surfaces of the conductive layer in the intersection direction (see e.g., first filling insulation pattern 16 includes an air gap region AG in the pixel isolation portion DTI between the first conductive pattern 14a and the second conductive pattern 14b in the intersection direction, Para [0060], Figure 4).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0238571 A1; hereafter Park) in view of Chiang et al. (US 2017/0133414 A1; hereafter Chiang).
Regarding claim 12, Park, as referred in claim 1, further teaches
wherein:
the pixel isolation portion further includes a third portion including the conductive layer and the inner layer between the first and second insulation portions in the intersection direction and (see e.g., as shown in modified Figure 3, third portion of the pixel isolation portion DTI between four pixels includes first conductive pattern 14a and the second conductive pattern 14b on the first and second portions of the insulating liner 12 and the first filling insulation pattern 16 is between first conductive pattern 14a and the second conductive pattern 14b, Paras [0052], [0053], Figure 4)
Park does not explicitly teach
“a third portion…having a width greater than a width of the second portion”.
In a similar field of endeavor Chiang teaches
a third portion…having a width greater than a width of the second portion (see e.g., the DTI grid 106 may have a first portion 106a between two adjacent image sensing elements (e.g. 104a and 104b) in the first direction X, such as a lateral direction or a vertical direction, and a second portion 106b between two image sensing elements (e.g. 104a and 104e) in the second direction Y, such as a diagonal direction. The first portion 106a has a first width w.sub.1 smaller than a second width w.sub.2 of the second portion 106b, Para [0018], Figures 1-3)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Chiang’s teachings of a third portion…having a width greater than a width of the second portion in the device of Park in order to improve overall pixel isolation.
Regarding claim 13, Park, as referred in claim 12, further teaches
wherein:
the first pixel region and the second pixel region are adjacent in a first direction,
the image sensor further includes a third pixel region and a fourth pixel region respectively adjacent to the first pixel region and the second pixel region in a second direction crossing the first direction, and (see e.g., Figure 3 shows an array of pixel regions PX)
the third portion is at a portion where the first to fourth pixel regions are adjacent to each other (see e.g., as shown in modified Figure 3 the third portion of the pixel isolation portion DTI is between four pixel regions PX).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0238571 A1; hereafter Park) in view of Chen et al. (US 2024/0222406 A1; hereafter Chen).
Regarding claim 18, Park teaches an image sensor (see e.g., image sensor, Figures 3-5 and 8-9), comprising:
a substrate including a plurality of pixel regions including a first pixel region and a second pixel region adjacent to each other (see e.g., first substrate 1 includes a pixel array region APS which includes a plurality of unit pixels UP adjacent to each, Para [0044], Figure 4);
a photoelectric converter at the substrate; and (see e.g., photoelectric conversion portion PD disposed in the first substrate 1, Para [0046], Figure 4)
a pixel isolation portion that separates the first pixel region and the second pixel region based on penetrating at least a part of the substrate between the first pixel region and the second pixel region (see e.g., pixel isolation portion DTI disposed in the first substrate 1 to isolate and /or define the unit pixels UP in the pixel array region APS, Para [0045], Figure 4),
wherein the pixel isolation portion includes
a first portion including first and second insulation portions respectively adjacent to the first and second pixel regions and a conductive layer that occupies a space defined between the first and second insulation portions in an intersection direction that intersects an extension direction of the pixel isolation portion, and (see e.g., portion of the pixel isolation portion DTI between two adjacent pixels regions PX, in a first direction, including insulating liner 12 includes first and second portions respectively adjacent to the first and second unit pixels UP, conductive structure 20, includes a first conductive pattern 14a, a second conductive pattern 14b and a connection conductive pattern 18, and first filling insulation pattern 16 between the first and second portions of the insulating liner 12, Paras (0052], [0053], Figure 4)
a second portion (see e.g., portion of the pixel isolation portion DTI between two adjacent pixels regions PX, in a second direction perpendicular to the first direction, including insulating liner 12 includes first and second portions respectively adjacent to the first and second unit pixels UP, conductive structure 20, includes a first conductive pattern 14a, a second conductive pattern 14b and a connection conductive pattern 18, and first filling insulation pattern 16 between the first and second portions of the insulating liner 12, Paras (0052], [0053], Figure 4)
Park does not explicitly teach
“a second portion having a width greater than a width of the first portion and a stacking structure different from a stacking structure of the first portion to have an electrical insulation structure”.
In a similar field of endeavor Chen teaches
a second portion having a width greater than a width of the first portion and a stacking structure different from a stacking structure of the first portion to have an electrical insulation structure (see e.g., first trench 119 including a linear layer 104 on the sidewalls and a conductive layer 111 within the linear layer 104. Second trench 129 including the linear layer 104, first conductive layer 121 and a second conductive layer 122 and, a dielectric layer 123 between the first conductive layer and the second conductive layer 122. As seen from figures the width of trench 119 is smaller than the width of trench 129, Paras [0073], [0083], Figures 2, 10-15).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chen’s teachings of a second portion having a width greater than a width of the first portion and a stacking structure different from a stacking structure of the first portion to have an electrical insulation structure in the device of Park in order to provide improved isolation structure.
Regarding claim 19, Park, as modified by Chen, teaches the limitations of claim 18 as mentioned above. Park further teaches
wherein:
the second portion includes the first and second insulation portions, first and second conductive portions respectively on the first and second insulation portions, and an inner layer between the first and second conductive portions (see e.g., the pixel isolation portion DTI includes a first conductive pattern 14a, second conductive pattern 14b and first filling insulation pattern 16 between the first and second portions of the insulating liner 12, Para [0053], Figure 4).
Regarding claim 20, Park, as modified by Chen, teaches the limitations of claim 19 as mentioned above. Park further teaches
wherein the inner layer includes an inner insulation layer including at least one of:
an insulating material, or
inner surfaces at least partially defining a space portion having an internal space between opposing surfaces of the conductive layer in the intersection direction (see e.g., the first filling insulation pattern 16 comprises silicon oxide and may also have an air gap, Para [0058], Figure 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAKEHA SEHAR whose telephone number is (571)272-4033. The examiner can normally be reached Monday-Thursday 7:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using
a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is available to
registered users. To file and manage patent submissions in Patent Center, visit:
https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more
information about Patent Center and https://www.uspto.gov/patents/docx for information about
filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at
866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service
Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights