DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-11, 13-14, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. Publication No. 2022/0381999 A1; hereinafter Chen)
With respect to claim 1, Chen discloses (in Figure 1) a semiconductor package comprising: a package substrate [130]; a plurality of stacked structures [180] on the package substrate (see ¶[0039]; a plurality of arrays of memory devices), each stacked structure including a plurality of core chips stacked on each other, each core chip including a memory cell array including a plurality of memory cells (see ¶[0028]); a buffer chip [190] on the package substrate and spaced apart from the plurality of stacked structures in a horizontal direction (see ¶[0040]); and a photonics package including an optical integrated circuit chip [192] on the package substrate, an electronic integrated circuit chip [194] on the optical integrated circuit chip, and a first molding layer [195] surrounding side surfaces of the electronic integrated circuit chip, wherein the buffer chip is configured to control the memory cells of the core chips of each of the plurality of stacked structures (see ¶[0039]).
With respect to claim 3, Chen discloses wherein: the package substrate is configured to transfer an electrical signal converted from the photonics package to the buffer chip, and the package substrate is configured to transfer electrical signals output by the plurality of stacked structures to the buffer chip (see ¶[0038]).
With respect to claim 4, Chen discloses wherein: the photonics package is electrically connected to a physical layer of the buffer chip via the package substrate, and the plurality of stacked structures are electrically connected to the buffer chip via the package substrate (see Figure 1 and ¶[0038]).
With respect to claim 5, Chen discloses a second molding layer [195] on the package substrate and surrounding side surfaces of the plurality of stacked structures, the buffer chip, and the photonics package (see Figure 1; molding layer [195] surrounds side surfaces of stacked structures, buffer chip and photonics package while also surrounding electronic integrated circuit chip (i.e., first molding layer) and [190] also includes ILD structures surrounded by [195]).
With respect to claim 6, Chen discloses a boundary surface between the first molding layer and the second molding layer (see ¶[0040]; ILD and [195]).
With respect to claim 7, Chen discloses wherein a top surface of the buffer chip is at the same vertical level above a bottom surface of the package substrate as a top surface of the photonics package (See Figure 1).
With respect to claim 8, Chen discloses wherein the optical integrated circuit chip further comprises a plurality of through vias [162] and a waveguide [145], and the waveguide is at an upper surface of the optical integrated circuit chip (see Figure 1; orientation has not been established by the claim language and therefore [194] can be interpreted as “at an upper surface of the optical integrated circuit chip” when viewed upon upside down in relation to presented drawing).
With respect to claim 10, Chen discloses a dummy chip on the buffer chip (see ¶[0040]; [190] can comprise multiple devices including active and passive devices).
With respect to claim 11, Chen discloses wherein a top surface of the dummy chip at the same vertical level above a bottom surface of the package substrate as a top surface of the photonics package (see Figure 1).
With respect to claim 13, Chen discloses a semiconductor package comprising: a package substrate [130]; a plurality of stacked structures [180] on the package substrate (see ¶[0039]; a plurality of arrays of memory devices), each stacked structure including a plurality of core chips stacked on each other, each core chip including a memory cell array including a plurality of memory cells (see ¶[0028]); a buffer chip [190] on the package substrate and spaced apart from the plurality of stacked structures in a horizontal direction (see ¶[0040]); and a photonics package including an optical integrated circuit chip [192] on the package substrate, an electronic integrated circuit chip [194] on the optical integrated circuit chip, and a first molding layer [195] surrounding side surfaces of the electronic integrated circuit chip (see ¶[0039]), wherein the buffer chip is configured to control the memory cells of the core chips of each of the plurality of stacked structures (see ¶[0038]), wherein the total number of buffer chips on the package substrate is less than the total number of stacked structures including the plurality of core chips stacked on each other on the package substrate (see Figure 1), and wherein the plurality of stacked structures and the photonics package are arranged to surround side surfaces of the buffer chip (see Figure 1).
With respect to claim 14, Chen discloses wherein the buffer chip is in a center region of the package substrate, and the plurality of stacked structures and the photonics package are on a periphery region of the package substrate (see Figure 1).
With respect to claim 16, Chen discloses wherein: a first side surface of the photonics package faces the buffer chip, and at least one of the plurality of stacked structures faces a second side surface adjacent to the first side surface of the photonics package (See Figure 1)
With respect to claim 17, Chen discloses at least one additional buffer chip (see ¶[0040]; [190] can comprise multiple devices including active and passive devices).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 12 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Schultz et al. (U.S. Publication No. 2025/0300146 A1; hereinafter Schultz)
With respect to claim 2, Chen fails to explicitly disclose wherein the plurality of core chips each include dynamic random access memory (RAM) (DRAM) memory cells. In the same field of endeavor, Schultz teaches wherein the plurality of core chips each include dynamic random access memory (RAM) (DRAM) memory cells (see ¶[0132]). Implementation of a DRAM memory within the memory stack of Chen, as taught by Schultz, would be obvious as DRAMs are common memory architectures well appreciated within the art with high bandwidth and low latency (see Schultz ¶[0132]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, Chen fails to disclose a heat sink on an upper portion of the buffer chip.
In the same field of endeavor, Schultz teaches a heat sink [160] on an upper portion of the buffer chip [110] (see figure 12). Implementation of a heat sink within the device of Chen, as taught by Schultz allows for increased management of heat dissipation from each chip structure (see Schultz ¶[0134]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 15, Chen discloses wherein one side surface among the side surfaces of the buffer chip faces the photonics package (see Figure 1), but fails to disclose the remaining side surfaces among the side surfaces of the buffer chip face the plurality of stacked structures
In the same field of endeavor, Schultz teaches an array of stack structures and buffer chips with stacked structures surrounding at least three of the four sides of the buffer chip (See Figure 1C). The array orientation of Schultz allows for maximizing of the chip space for increasing capability and storage of the device (See Figure 1C). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Winzer et al. (U.S. Publication No. 2024/0097796 A1; hereinafter Winzer)
With respect to claim 9, Chen fails to disclose wherein the first molding layer of the photonics package further comprises an opening portion extending from an upper surface of the first molding layer inward, and the opening portion of the first molding layer is above a portion of the waveguide of the optical integrated circuit chip. In the same field of endeavor, Winzer teaches wherein the first molding layer of the photonics package further comprises an opening portion extending from an upper surface of the first molding layer inward, and the opening portion of the first molding layer is above a portion of the waveguide of the optical integrated circuit chip (See Figure 17; [522]).
Implementation of an opening portion within the waveguide portion of the optical integrated circuit chip as taught by Winzer allows for proper attachment of the optical fiber structure into the optical integrated circuit chip (see ¶[0332]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Schultz and Winzer.
With respect to claim 18, Chen discloses a semiconductor package comprising: a package substrate [130]; a plurality of stacked structures [180] on the package substrate (see ¶[0039]; a plurality of arrays of memory devices), each stacked structure including a plurality of core chips stacked on each other, each core chip including memory cells (see ¶[0028]); a buffer chip [190] on the package substrate and spaced apart from the plurality of stacked structures (see ¶[0040]); a photonics package including an optical integrated circuit chip [192] on the package substrate, an electronic integrated circuit chip [194] on the optical integrated circuit chip, and a first molding layer [195] surrounding side surfaces of the electronic integrated circuit chip (see ¶[0039]); and a second molding layer on the package substrate and surrounding side surfaces of the plurality of stacked structures, the buffer chip, and the photonics package (see Figure 1; molding layer [195] surrounds side surfaces of stacked structures, buffer chip and photonics package while also surrounding electronic integrated circuit chip (i.e., first molding layer) and [190] also includes ILD structures surrounded by [195]), wherein the buffer chip is configured to control the memory cells of the core chips of each of the plurality of stacked structures (see ¶[0038]), wherein the plurality of stacked structures and the photonics package are arranged to surround side surfaces of the buffer chip (see Figure 1)
Chen fails to disclose each core chip including dynamic random access memory (RAM) (DRAM) memory cells, or wherein the first molding layer of the photonics package comprises an opening portion extending from an upper surface of the first molding layer inward. In the same field of endeavor, Schultz teaches wherein each core chip include dynamic random access memory (RAM) (DRAM) memory cells (see ¶[0132]). Furthermore, Winzer teaches wherein the first molding layer of the photonics package comprises an opening portion extending from an upper surface of the first molding layer inward (See Figure 17; [522]). Implementation of a DRAM memory within the memory stack of Chen, as taught by Schultz, would be obvious as DRAMs are common memory architectures well appreciated within the art with high bandwidth and low latency (see Schultz ¶[0132]). Additionally, implementation of an opening portion within the waveguide portion of the optical integrated circuit chip as taught by Winzer allows for proper attachment of the optical fiber structure into the optical integrated circuit chip (see ¶[0332]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 19, the combination of Chen, Schultz and Winzer discloses wherein a top surface of the first molding layer and a top surface of the second molding layer are coplanar surfaces with each other, and wherein a boundary surface is between the first molding layer and the second molding layer (see Chen Figure 1 and ¶[0040]; ILD and [195]).
With respect to claim 20, the combination of Chen, Schultz and Winzer discloses wherein a first side surface among the side surfaces of the buffer chip faces the photonics package, and remaining side surfaces among the side surfaces of the buffer chip face the plurality of stacked structures (See Schultz Figure 1C). The array orientation of Schultz allows for maximizing of the chip space for increasing capability and storage of the device (See Schultz Figure 1C). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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