DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,430,083 to Lu et al. (hereafter Lu).
Regarding independent claim 1, Lu teaches a random access memory comprising:
a set of loops of inverters (multi-banked register files of FIG. 8 comprises plurality of register-file cells illustrated in FIG. 4), wherein the loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses (see 2:41-47);
an inherent write circuit configured to write a value to a first loop of inverters (FIG. 4: inherent write circuit to provide data at write data input 450) when provided with a corresponding address for the first loop of inverters, wherein the first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses; and
an inherent read circuit configured to read the value from the first loop of inverters (FIG. 4: inherent read circuit to receive data at read data output 440) when provided with the corresponding address.
Regarding dependent claim 2, Lu teaches wherein: the random access memory is integrated with a processor; the processor conducts computations using a set of logic transistors; the loops of inverters are formed by a set of inverter transistors; and the set of logic transistors and the set of inverter transistors are formed using a common process flow (see 1:9-25 and 2:16-58).
Regarding dependent claim 3, Lu teaches wherein: the random access memory is integrated with a processor; the processor conducts computations using a set of logic transistors; the loops of inverters are formed by a set of inverter transistors; and the set of logic transistors and the set of inverter transistors are field effect transistors (see 1:9-25 and 2:16-58).
Regarding dependent claim 4, Lu teaches wherein: the inverters in the loops of inverters each comprise two complementary field effect transistors (because it is how inverter is formed).
Regarding dependent claim 6, Lu teaches wherein: the write circuit is configured to write the value to the first loop of inverters by implicitly forcing the first loop of inverters into an oscillation state; and the read circuit is configured to read the value from the first loop of inverters by detecting the oscillation state of the first loop of inverters (FIG. 6: data write into and read from the register of FIG. 6 is oscillated by feedback control signal 605, swap control signals 685 and 640).
Regarding dependent claim 7, Lu implicitly teaches wherein: the read circuit is configured to read the value from the first loop of inverters by detecting a pattern of pulses on the first loop of inverters (detecting pattern of pulses is a should because there’s one read output 630 for different data paths).
Regarding independent claim 20, Lu teaches a random access memory comprising:
an array of loops of inverters (multi-banked register files of FIG. 8 comprises plurality of register-file cells illustrated in FIG. 4) wherein the loops of inverters in the array of loops of inverters are independently readable and independently writable using a set of corresponding addresses (see 2:41-47);
an inherent means for writing values to the loops of inverters independently using the set of corresponding addresses (FIG. 4: inherent write circuit to provide data at write data input 450); and
an inherent means for reading the values from the loops of inverters independently using the set of corresponding addresses (FIG. 4: inherent read circuit to receive data at read data output 440).
Claims 1-5, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,093,135 to Khailany et al. (hereafter Khailany).
Regarding independent claim 1, Khailany teaches a random access memory comprising:
a set of loops of inverters (register file of FIG. 3, which comprises plurality of loops of inverters, each is illustrated in FIG. 2), wherein the loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses (see 4:6-15);
a write circuit configured to write a value to a first loop of inverters (FIG. 3: e.g. local write bit line driver WDrv 320A) when provided with a corresponding address for the first loop of inverters, wherein the first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses (FIG. 3: e.g. when the storage cell is selected by corresponding write word line); and
a read circuit configured to read the value from the first loop of inverters (FIG. 3: e.g. local read bit line driver RDrv) when provided with the corresponding address (FIG. 3: e.g. when the storage cell is selected by corresponding read word line).
Regarding dependent claim 2, Khailany teaches wherein: the random access memory is integrated with a processor; the processor conducts computations using a set of logic transistors; the loops of inverters are formed by a set of inverter transistors; and the set of logic transistors and the set of inverter transistors are formed using a common process flow (see field of the invention, background and FIG. 2).
Regarding dependent claim 3, Khailany teaches wherein: the random access memory is integrated with a processor; the processor conducts computations using a set of logic transistors; the loops of inverters are formed by a set of inverter transistors; and the set of logic transistors and the set of inverter transistors are field effect transistors (see field of the invention, background and FIG. 2).
Regarding dependent claim 4, Khailany teaches wherein: the inverters in the loops of inverters each inherently comprise two complementary field effect transistors (see FIG. 2).
Regarding dependent claim 5, Khailany teaches wherein the loops of inverters in the set of loops of inverters each consist of an odd number of inverters (two inverters of FIG. 2 and an inverter in the DWrv cell 320A of FIG. 3, see 4:23-31).
Regarding independent claim 20, Khailany teaches a random access memory comprising:
an array of loops of inverters (register file of FIG. 3, which comprises plurality of loops of inverters, each is illustrated in FIG. 2) wherein the loops of inverters in the array of loops of inverters are independently readable and independently writable using a set of corresponding addresses (see 4:6-15);
a means for writing values to the loops of inverters independently (FIG. 3: e.g. local write bit line driver WDrv 320A) using the set of corresponding addresses (FIG. 3: e.g. when the storage cell is selected by corresponding write word line); and
a means for reading the values from the loops of inverters independently (FIG. 3: e.g. local read bit line driver RDrv) using the set of corresponding addresses (FIG. 3: e.g. when the storage cell is selected by corresponding read word line).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Khailany in view of US 11,887,002 to Park et al. (hereafter Park).
Khailany teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 14, Park teaches an encoding neural network that forms part of the write circuit; and a decoding neural network that forms part of the read circuit (FIG. 4: latent vector layer 420 between encoder 410 as input and decoder 430 as output. It is seen that the latent vector layer 420 is register layer).
Since Khailany and Park are both from the same field of endeavor, the purpose disclosed by Khailany would have been recognized in the pertinent art of Park.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the register cells of Khailany for neural network of Park because register cells have many uses.
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Khailany in view of Lu.
Regarding independent claim 15, Khailany teaches a random access memory comprising:
an array of loops of inverters (register file of FIG. 3, which comprises plurality of loops of inverters, each is illustrated in FIG. 2) wherein the loops of inverters in the array of loops of inverters are independently readable and independently writable using a set of corresponding addresses (see 4:6-15);
at least one write circuit (FIG. 3: e.g. local write bit line driver WDrv 320A) configured to set an FIG. 3: e.g. when the storage cell is selected by corresponding write word line); and
at least one read circuit (FIG. 3: e.g. local read bit line driver RDrv) configured to sense the FIG. 3: e.g. when the storage cell is selected by corresponding read word line).
Khailany is silent the write/read state is an write/read oscillation state.
Lu teaches a register cell of FIG. 6 comprising loop of inverters. It is obvious that data written into or read data from the register cell is oscillated by feedback control signal 605, swap control signals 685 and 640.
Since Khailany and Lu are both from the same field of endeavor, the purpose disclosed by Lu would have been recognized in the pertinent art of Khailany.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace the register cell of Lu with that of Khailany
for high bandwidth and efficiency in operation (see Khailany, 1:10-30).
Regarding dependent claim 16, Khailany teaches wherein: the random access memory is integrated with a processor; the processor conducts computations using a set of logic transistors; the loops of inverters are formed by a set of inverter transistors; and the set of logic transistors and the set of inverter transistors are formed using a common process flow (see field of the invention, background and FIG. 2).
Regarding dependent claim 17, Khailany teaches wherein: the random access memory is integrated with a processor; the processor conducts computations using a set of logic transistors; the loops of inverters are formed by a set of inverter transistors; and the set of logic transistors and the set of inverter transistors are field effect transistors (see field of the invention, background and FIG. 2).
Regarding dependent claim 18, Khailany teaches wherein: the inverters in the loops of inverters each comprise two complementary field effect transistors (see FIG. 2).
Regarding dependent claim 19, Khailany teaches wherein: the loops of inverters in the array of loops of inverters each consist of an odd number of inverters (two inverters of FIG. 2 and an inverter in the DWrv cell 320A of FIG. 3, see 4:23-31).
Allowable Subject Matter
Claims 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 8: wherein: the read circuit is configured to read the value from the first loop of inverters by measuring a pulse width of a pulse from the loop of inverters.
With respect to dependent claim 12: a memory array voltage regulator that provides a memory supply voltage to the loops of inverters in the set of loops of inverters; wherein the random access memory is integrated with a processor having logic transistors, and a supply voltage for the logic transistors of the processor is greater than the memory supply voltage.
With respect to dependent claim 13: a memory array voltage regulator that provides a memory supply voltage to the loops of inverters in the set of loops of inverters; and a pair of transistors that form part of an inverter in the loops of inverters, wherein the pair of transistors have a pair of threshold voltage; wherein the memory supply voltage is equal to or less than a sum of the pair of threshold voltages.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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January 5, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824