Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 2021/0057300 A1), hereinafter as Y1, in view of Fish et al. (US 2015/0241631 A1), hereinafter F1.
Regarding Claim 1, Y1 discloses an electronic package (see FIGs. 2A-2E, element 2, and see [0037] ln. 1 “FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating an electronic package 2 according to the present disclosure”), comprising:
an electronic module (see FIG. 2E, elements, 20, 21, and 21’, [0041] ln. 1 “first electronic component 21, 21′” and [0047] ln. 1 “circuit structure 20” which together form an electronic module);
an optoelectronic component (see FIG. 2E, element 26, and [0052] ln. 1 “optoelectronic component 26”) disposed on and electrically connected to the electronic module (see [0050] ln. 6 “optoelectronic component 26 are disposed on the circuit structure 20” and [0053] ln. 2 “optoelectronic component 26 is electrically connected to the conductive pads 202 via a plurality of conductive bumps 27” where it can be seen in FIG. 2E are connected to the circuit structure 20); and
Y1 does not explicitly disclose a lens module disposed on a side of the optoelectronic component.
F1 discloses a lens module (see FIG. 2B, element 220, and [0024] ln. 1 “a lens unit 220”) disposed on a side of the optoelectronic component (see FIG. 2B, element 200, and [0023] ln. 3 “a PIC {Photonic Integrated Circuit} 200”) which is a known optoelectronic component, also see the lens module 220 is disposed on a side of the optoelectronic device 200).
The optoelectronic component as disclosed by F1 is integrated into the disclosure Y1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of F1 into Y1 as there is motivation to include a lens on the optoelectronic component to replace the need of a cable (or other optical fiber) to be attached and supported within the device. Using optical transmission over electrical connection could predictably increase the speed of information transfer, and by including a lens module for this purpose, the need for further cable support and construction is forgone. Using a lens module within an optoelectronic component yields predictable results (see F1 [0028-0029]).
Regarding Claim 2, Y1 and F1 disclose the electronic package of claim 1, wherein Y1 further discloses the electronic module (elements 20, 21, and 21’) includes an electronic component that is electrically connected to the optoelectronic component (as disclosed prior, the optoelectronic component is connected to the circuit structure 20 of the described electronic module through the conductive pads 202 via a plurality of conductive bumps 27 as seen in FIG. 2E).
Regarding Claim 3, Y1 and F1 disclose the electronic package of claim 2, wherein Y1 further discloses the electronic component (elements 20, 21, and 21’) is an electronic IC (EIC) (As a part of the described electronic component, the circuit structure 20 itself is an integrated circuit and therefore a part of an electronic integrated circuit that makes up the electronic component).
Regarding Claim 4, Y1 and F1 disclose the electronic package of claim 1, wherein F1 further discloses the optoelectronic component (element 200) is a photonic IC (PIC) (see [0023] ln. 3 “a PIC 200” where the element is described as such).
Regarding Claim 7, Y1 discloses a manufacturing method of an electronic package (see FIGs. 2A-2E, element 2, and see [0037] ln. 1 “FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating an electronic package 2 according to the present disclosure”), comprising:
providing an electronic module (see FIG. 2E, elements, 20, 21, and 21’, [0041] ln. 1 “first electronic component 21, 21′” and [0047] ln. 1 “circuit structure 20” which together form an electronic module);
disposing an optoelectronic component (see FIG. 2E, element 26, and [0052] ln. 1 “optoelectronic component 26”) on the electronic module and electrically connecting the optoelectronic component to the electronic module (see [0050] ln. 6 “optoelectronic component 26 are disposed on the circuit structure 20” and [0053] ln. 2 “optoelectronic component 26 is electrically connected to the conductive pads 202 via a plurality of conductive bumps 27” where it can be seen in FIG. 2E are connected to the circuit structure 20); and
Y1 does not explicitly disclose disposing a lens module on a side of the optoelectronic component.
F1 disposing a lens module (see FIG. 2B, element 220, and [0024] ln. 1 “a lens unit 220”) on a side of the optoelectronic component (see FIG. 2B, element 200, and [0023] ln. 3 “a PIC {Photonic Integrated Circuit} 200”) which is a known optoelectronic component, also see the lens module 220 is disposed on a side of the optoelectronic device 200).
The optoelectronic component as disclosed by F1 is integrated into the disclosure Y1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of F1 into Y1 as there is motivation to include a lens on the optoelectronic component to replace the need of a cable (or other optical fiber) to be attached and supported within the device. Using optical transmission over electrical connection could predictably increase the speed of information transfer, and by including a lens module for this purpose, the need for further cable support and construction is forgone. Using a lens module within an optoelectronic component yields predictable results (see F1 [0028-0029]).
Regarding Claim 8, Y1 and F1 disclose the manufacturing method of claim 7, wherein Y1 further discloses the electronic module (elements 20, 21, and 21’) includes an electronic component that is electrically connected to the optoelectronic component (as disclosed prior, the optoelectronic component is connected to the circuit structure 20 of the described electronic module through the conductive pads 202 via a plurality of conductive bumps 27 as seen in FIG. 2E).
Regarding Claim 9, Y1 and F1 disclose the manufacturing method of claim 8, wherein Y1 further discloses the electronic component (elements 20, 21, and 21’) is an electronic IC (EIC) (As a part of the described electronic component, the circuit structure 20 itself is an integrated circuit and therefore a part of an electronic integrated circuit that makes up the electronic component).
Regarding Claim 10, Y1 and F1 disclose the manufacturing method of claim 7, wherein F1 further discloses the optoelectronic component (element 200) is a photonic IC (PIC) (see [0023] ln. 3 “a PIC 200” where the element is described as such).
Claims 5, 6, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over You et al. (US 2021/0057300 A1), hereinafter as Y1, and Fish et al. (US 2015/0241631 A1), hereinafter F1, in view of Zhang et al. (US 2021/0141172 A1), hereinafter as Z1.
Regarding Claim 5, Y1 and F1 disclose the electronic package of claim 1, wherein F1 further discloses the optoelectronic component (element 200) has a recess (see FIG. 2B, element 251, and [0028] ln. 7 “a hole 251”), such that a portion of the lens module (element 220) is accommodated within the recess (see FIG. 2B where the lens unit 220 is within the hole 251) and
Y1 and F1 do not disclose another portion of the lens module bulges out from the recess.
Z1 discloses another portion of the lens module bulges out from the recess (see FIG.1, elements 100 and 110, and [0045] ln. 1 “an optoelectronic device 100….a mirror, and specifically a micro-mirror, 110 is located within the cavity” where the lens is recessed in the cavity and also protrudes out of it).
The lens as disclosed by Z1 is incorporated into the disclosure of Y1 and F1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of Z1 into Y1 and F1 as there is motivation to have the lens imbedded into the PIC for structural support while still having the lens outside the PIC for transmission of light. Having the lens integrated into the PIC while still extending outward, the electronic component can transmit optical signals while supporting the lens, which yields predictable results (see Z1 [0014-0015]).
Regarding Claim 6, Y1, F1, and Z1 disclose the electronic package of claim 5, wherein F1 further discloses the recess is formed on a top side or a bottom side of the optoelectronic component (see FIG. 2B where the hole 251 is formed at the top of the optoelectronic component 200).
Regarding Claim 11, Y1 and F1 disclose the manufacturing method of claim 7, wherein F1 further discloses the optoelectronic component (element 200) has a recess (see FIG. 2B, element 251, and [0028] ln. 7 “a hole 251”), such that a portion of the lens module (element 220) is accommodated within the recess (see FIG. 2B where the lens unit 220 is within the hole 251) and
Y1 and F1 do not disclose another portion of the lens module bulges out from the recess.
Z1 discloses another portion of the lens module bulges out from the recess (see FIG.1, elements 100 and 110, and [0045] ln. 1 “an optoelectronic device 100….a mirror, and specifically a micro-mirror, 110 is located within the cavity” where the lens is recessed in the cavity and also protrudes out of it).
The lens as disclosed by Z1 is incorporated into the disclosure of Y1 and F1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of Z1 into Y1 and F1 as there is motivation to have the lens imbedded into the PIC for structural support while still having the lens outside the PIC for transmission of light. Having the lens integrated into the PIC while still extending outward, the electronic component can transmit optical signals while supporting the lens, which yields predictable results (see Z1 [0014-0015]).
Regarding Claim 12, Y1, F1, and Z1 disclose the manufacturing method of claim 11, wherein F1 further discloses the recess is formed on a top side or a bottom side of the optoelectronic component (see FIG. 2B where the hole 251 is formed at the top of the optoelectronic component 200).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights