DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/11/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: THREE-DIMENSIONAL SEMICONDUCTOR DEVICE INCLUDING CONTACT PLUGS AND METHOD OF MANUFACTURING THE SAME
Allowable Subject Matter
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device wherein “a contact surface is formed between the protruding portion of each of the conductive contact plugs and a sidewall of the corresponding conductive pattern, and wherein the contact surface is located between two neighboring interlayer insulating layers in the first direction among the interlayer insulating layers” as recited in claim 3 in combination with the rest of the limitations of claims 1-2; and a semiconductor device wherein “each of the conductive contact plugs is formed deeper than a corresponding spacer insulating layer among the spacer insulating layers” as recited in claim 4 in combination with the rest of the limitations of claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 and 5-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 9,577,085. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-2 and 5 of the current application is broader than and anticipated by claim 2 (claims 1+2) of patent no. 9,577,085. See claim to claim comparison below. Regarding claim 1, patent no. 9,577,085 teaches a semiconductor device, comprising: conductive patterns stacked in a first direction and spaced apart from each other; interlayer insulating layers arranged alternately with the conductive patterns in the first direction (A semiconductor device, comprising: interlayer insulating layers stacked in a first direction and separated from each other; word lines formed between the interlayer insulating layers) (claim1), the interlayer insulating layers extending to protrude more laterally than sidewalls of the conductive patterns; conductive contact plugs passing through an uppermost interlayer insulating layer among the interlayer insulating layers (cell contact plugs … passing through at least one of the interlayer insulating layers) (claim 1) and extending at different depths (wherein the cell contact plugs have different depths) (claim 1) to respectively contact the sidewalls of the conductive patterns (a first protruding portion … contacting a sidewall of one of the word lines) (claim 1); and spacer insulating layers respectively surrounding sidewalls of the conductive contact plugs (a spacer insulating layer surrounding the first pillar portion) (claim 2) and spaced apart from the conductive patterns (patent no. 9,577,085, claims 1 and 2). Regarding claim 2, patent no. 9,577,085 teaches a semiconductor device wherein each of the conductive contact plugs includes a pillar portion (cell contact plugs each including a first pillar portion) (claim 1) surrounded by a corresponding spacer insulating layer among the spacer insulating layers (a spacer insulating layer surrounding the first pillar portion) (claim 2) and a protruding portion extending from the pillar portion to contact a corresponding conductive pattern among the conductive patterns (cell contact plugs each including … a first protruding portion protruding from a lower sidewall of the first pillar portion to surround the lower sidewall of the first pillar portion and contacting a sidewall of one of the word lines) (claim 1) (patent no. 9,577,085, claims 1 and 2). Regarding claim 5, patent no. 9,577,085 teaches a semiconductor device comprising sacrificial insulating layers interposed between the conductive patterns and the spacer insulating layers (sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed) (claim 1) (patent no. 9,577,085, claims 1 and 2). Regarding claim 6, patent no. 9,577,085 teaches a semiconductor device wherein each of the sacrificial insulating layers is located between two neighboring interlayer insulating layers in the first direction among the interlayer insulating layers (sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed) (claim 1) (patent no. 9,577,085, claims 1 and 2). Regarding claim 7, patent no. 9,577,085 teaches a semiconductor device wherein the conductive contact plugs include a cell contact plug contacting a word line among the conductive patterns (cell contact plugs … contacting a sidewall of one of the word lines) (claim 1), wherein the cell contact plug includes a pillar portion (cell contact plugs each including a first pillar portion) (claim 1) surrounded by a corresponding spacer insulating layer among the spacer insulating layers (a spacer insulating layer surrounding the first pillar portion) (claim 2) and a protruding portion extending from the pillar portion to contact a sidewall of the word line (cell contact plugs each including … a first protruding portion protruding from a lower sidewall of the first pillar portion to surround the lower sidewall of the first pillar portion and contacting a sidewall of one of the word lines) (claim 1), and wherein the protruding portion of the cell contact plug is located between two neighboring sacrificial insulating layers in the first direction among the sacrificial insulating layers (sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed) (claim 1) (patent no. 9,577,085, claims 1 and 2).
Current Application 18/770,150
Patent No. 9,577,085
1. A semiconductor device, comprising: conductive patterns stacked in a first direction and spaced apart from each other; interlayer insulating layers arranged alternately with the conductive patterns in the first direction, the interlayer insulating layers extending to protrude more laterally than sidewalls of the conductive patterns; conductive contact plugs passing through an uppermost interlayer insulating layer among the interlayer insulating layers and extending at different depths to respectively contact the sidewalls of the conductive patterns; and spacer insulating layers respectively surrounding sidewalls of the conductive contact plugs and spaced apart from the conductive patterns.2. The semiconductor device of claim 1, wherein each of the conductive contact plugs includes a pillar portion surrounded by a corresponding spacer insulating layer among the spacer insulating layers and a protruding portion extending from the pillar portion to contact a corresponding conductive pattern among the conductive patterns.5. The semiconductor device of claim 1, further comprising sacrificial insulating layers interposed between the conductive patterns and the spacer insulating layers.
1. A semiconductor device, comprising: interlayer insulating layers stacked in a first direction and separated from each other; word lines formed between the interlayer insulating layers; sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed; and cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the a first protruding portion protruding from a lower sidewall of the first pillar portion to surround the lower sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths.2. The semiconductor device of claim 1, further comprising a spacer insulating layer surrounding the first pillar portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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