DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II in the reply filed on 02/18/2026 is acknowledged. Applicant’s argument with respect to claim 11 is persuasive. Species II, now including claims 1, 11-13, 16-18, is examined. Species I, claims 2-10 and 14-15, is withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11-13, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 7,253,496 to Jenne et al. (hereafter Jenne) in view of US 8,643,100 to Ito (hereafter Ito).
Regarding independent claim 1, Jenne teaches a one-time programmable memory cell comprising:
a transistor comprising a drain, a source and a channel between the drain and the source, the transistor being connected to a data storage element and to a memory cell selection element (FIGS. 5 and 7: transistor Q8 being connected to antifuse 710 and select transistor Q7),
Jenne does not teach the strikethrough limitations.
Ito teaches a transistor comprising a drain, a source and a channel between the drain and the source, wherein the channel of the transistor comprises a first and a second channel portion, a dopant concentration in the first channel portion being higher than in the second channel portion (see FIGS. 5-6, 7:40-49 and 8:34-54).
Since Jenne and Ito are both from the same field of endeavor, the purpose disclosed by Jenne would have been recognized in the pertinent art of Ito.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace transistor Q8 of Jenne with that in FIG. 6 of Ito in order to increase reliability, since the transistor in FIG. 6 of Ito has ability to interface between antifuse 710 of high operating voltage and transistor Q7 of low operating voltage of Jenne (see 1:14-52).
Regarding dependent claim 11, Jenne teaches wherein the memory cell selection element comprises a further transistor (FIG. 7: select transistor Q7).
Regarding dependent claim 12, Jenne teaches wherein an operating voltage of the further transistor is equal to 1.8V instead of equal to or less than 1.2V (see 4:54-5:13).
However, Ito suggests, with the use of transistor of FIG. 6, there is possibility that select transistor may scale down more and operating voltage may set equal to or less than 1.2V (see 1:14-52).
Regarding dependent claim 13, Jenne teaches wherein the data storage element is configured to be programmable by applying a programming voltage, the programming voltage being higher than an operating voltage of the further transistor, and wherein the programming voltage applied to the further transistor would damage the further transistor (see 2:55-3:17).
Regarding dependent claim 16, Jenne further teaches a method of programming or reading the memory cell comprising: applying a selection voltage to the memory cell selection element (FIG. 7: e.g. Vsel of 1.8V, see 4:54-5:13); applying a blocking voltage to a gate of the transistor (FIG. 7: e.g. VBlock of 3.3V, see 2:62-65 and 4:36), and applying a programming (FIG. 7: Vprogram of 7.5V, see 4:54-5:13) or a reading voltage to the data storage element to program or read the selected memory cell, wherein the blocking voltage is larger than the selection voltage and lower than the programming voltage.
Regarding dependent claim 17, Jenne and Ito teaches a memory device comprising the memory cell according to claim 1 (such as integrated circuit, see 1:20-34).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jenne in view of Ito in view of US 10,930,359 to Rachinsky et al. (hereafter Rachinsky).
Jenne and Ito teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim.
Regarding dependent claim 18, Rachinsky teaches a memory device comprising a first, second, third and fourth memory cell (FIG. 2: memory cells 201-204), the memory cell selection element of each memory cell comprising a respective further transistor comprising a gate (FIG. 2: select transistor M of each of memory cells 201-204); a shared data line for applying a programming or reading voltage, the shared data line being connected to the data storage element of each memory cell (FIG. 2: D line); FIG. 1: S1 line connected to memory cells 201 and 203), the second selection line being connected to the further transistor of the second memory cell and to the further transistor of the fourth memory cell (FIG. 1: S1 line connected to memory cells 202 and 204), and a first and second word line, the first word line being connected to the gate of the further transistor of the first memory cell and to the gate of the further transistor of the second memory cell (FIG. 1: WL1 line connected to memory cells 201 and 202), the second word line being connected to the gate of the further transistor of the third memory cell and to the gate of the further transistor of the fourth memory cell (FIG. 1: WL2 line connected to memory cells 203 and 204), and wherein the device is arranged such at least one of the four memory cells is selectable for programming or reading by applying a voltage to at least one of the selection and word lines (see 2:40-42).
Since Jenne, Ito and Rachinsky are all from the same field of endeavor, the purpose disclosed by Rachinsky would have been recognized in the pertinent art of Jenne and Ito.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
replace the OTP memory cells of Rachinsky with that of Renne and Ito in order to increase reliability.
realize that blocking lines should be included for OTP memory cells of Renne and Ito.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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March 18, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824