Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: amendment filed on March 31, 2026.
This application has been examined. Claims 1-20 are pending.
Double Patenting
4. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-4, 5-6, 7-8, 10, 11-12, 13, 14-15, 16, 17, 18, 19, 20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-4, 6, 5, 7-8, 10, 12-13, 11, 14-15, 18, 16, 19 17, 20 in Patent No. 12,045,106, respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-4, 6, 5, 7-8, 10, 12-13, 11, 14-15, 18, 16, 19 17, 20 of the US Patent No. 12,045,106 are similar in scope to claims 1-4, 5-6, 7-8, 10, 11-12, 13, 14-15, 16, 17, 18, 19, 20 of the present application with only obvious wording variations. See table.
PRESENT APPLICATION
PAT NO. 12,045,106
1. A method comprising: in response to detecting a reset condition at a virtual function of a virtual machine executing at a processing system, initiating a reset sequence for a processing portion of a processing unit associated with the virtual function, wherein the initiating bypasses a host driver of the processing system.
2. The method of claim 1, wherein the reset sequence includes a handshake between a local system management unit (SMU) of the processing unit and a device driver of the virtual machine.
3. The method of claim 1, wherein the initiating bypasses a hypervisor of the processing system.
4. The method of claim 1, wherein the processing unit comprises a plurality of semiconductor dies, and wherein the processing portion of the processing unit comprises one of the plurality of semiconductor dies.
5. The method of claim 4, wherein the reset sequence comprises a reset sequence to reset the one of the plurality of semiconductor dies independent of resetting other semiconductor dies of the plurality of semiconductor dies.
6. The method of claim 1, wherein the processing unit is spatially partitioned into a plurality of processing portions, wherein the plurality of processing portions comprises the processing portion.
7. The method of claim 6, wherein each of the plurality of processing portions is assigned to a different one of a plurality of virtual functions, wherein the plurality of virtual functions comprises the virtual function.
8. A non-transitory computer readable medium tangibly embodying a set of instructions to manipulate a processor, the instructions comprising instructions to: in response to detecting a reset condition at a virtual function of a virtual machine, initiate a reset sequence for a processing portion of a processing unit, wherein the initiating of the reset sequence bypasses a host driver.
10. The non-transitory computer readable medium of claim 8, wherein the processing unit comprises a graphics processing unit (GPU).
11. The non-transitory computer readable medium of claim 10, wherein the GPU comprises a plurality of GPU chiplets, and wherein the processing portion corresponds to one of the plurality of GPU chiplets.
12. The non-transitory computer readable medium of claim 11, wherein the processing portion comprises a render engine assigned to the virtual machine.
13. The non-transitory computer readable medium of claim 8, wherein the reset condition comprises a detected error at the processing portion of the processing unit.
14. A processing system, comprising: a processing unit; and a processor to execute a virtual machine and a virtual function associated with the virtual machine, wherein in response to detecting a reset condition, the processing unit initiates a reset sequence for a processing portion of the processing unit associated with the virtual function, wherein the initiating of the reset sequence bypasses a host driver of the processing system.
15. The processing system of claim 14, wherein the reset sequence includes a handshake between a local system management unit (SMU) of the processing unit and a device driver of the virtual machine.
16. The processing system of claim 15, wherein the initiating of the reset sequence bypasses a hypervisor of the processing system.
17. The processing system of claim 14, wherein the processing unit comprises a plurality of semiconductor dies, and wherein the processing portion of the processing unit comprises one of the plurality of semiconductor dies.
18. The processing system of claim 17, wherein the reset sequence comprises a reset sequence to reset the one of the plurality of semiconductor dies independent of other semiconductor dies of the plurality of semiconductor dies.
19. The processing system of claim 14, wherein the processing unit is spatially partitioned into a plurality of processing portions, wherein the plurality of processing portions comprises the processing portion.
20. The processing system of claim 19, wherein each of the plurality of processing portions is assigned to a different one of a plurality of virtual functions, wherein the plurality of virtual functions comprises the virtual function.
1. A method comprising:
2. The method of claim 1, wherein the reset sequence includes a handshake between the local SMU and a device driver of the virtual machine.
3. The method of claim 1, wherein the initiating bypasses a hypervisor of the processing system.
4. The method of claim 1, wherein the processing unit comprises a plurality of semiconductor dies, and wherein the processing portion of the processing unit comprises one of the plurality of semiconductor dies.
6. The method of claim 4, wherein the reset sequence comprises a reset sequence to reset the one of the plurality of semiconductor dies independent of resetting other semiconductor dies of the plurality of semiconductor dies.
5. The method of claim 1, wherein the processing unit is spatially partitioned into a plurality of processing portions comprising the processing portion.
7. The method of claim 5, wherein each of the plurality of processing portions is assigned to a different one of a plurality of virtual functions comprising the virtual function.
8. A non-transitory computer readable medium tangibly embodying a set of instructions to manipulate a processor, the instructions comprising instructions to: in response to detecting a reset condition at a virtual function of a virtual machine, initiate a reset sequence for a processing portion of a processing unit; and responsive to initiating the reset sequence, execute a handshake between a local system management unit (SMU) of the processing unit and a local device driver of the virtual machine.
10. The non-transitory computer readable medium of claim 8, wherein the processing unit comprises a graphics processing unit (GPU).
12. The non-transitory computer readable medium of claim 10, wherein the GPU comprises a plurality of GPU chiplets, and wherein the processing portion corresponds to one of the plurality of GPU chiplets.
13. The non-transitory computer readable medium of claim 12, wherein the processing portion comprises a render engine assigned to the virtual machine.
11. The non-transitory computer readable medium of claim 8, wherein the reset condition comprises a detected error at the processing portion of the processing unit.
14. A processing system, comprising: a processing unit; and a processor to execute a virtual machine and a virtual function associated with the virtual machine, wherein in response to detecting a reset condition,
15. The processing system of claim 14, wherein the reset sequence includes a handshake between the local SMU and a device driver of the virtual machine.
18. The processing system of claim 15, wherein the reset sequence bypasses a hypervisor of the processing system.
16. The processing system of claim 14, wherein the processing unit comprises a plurality of semiconductor dies, and wherein the processing portion of the processing unit comprises one of the plurality of semiconductor dies.
19. The processing system of claim 16, wherein the reset sequence comprises a reset sequence to reset the one of the plurality of semiconductor dies independent of other semiconductor dies of the plurality of semiconductor dies.
17. The processing system of claim 14, wherein the processing unit is spatially partitioned into a plurality of processing portions.
20. The processing system of claim 17, wherein each of the plurality of processing portions is assigned to a different one of a plurality of virtual functions.
In re Karlson, 136 USPQ 189 (ccPA 1963).
Allowable Subject Matter
6. Claims 1-20 are allowable over the prior of records.
Response to Amendment
7. Applicant’s amendment and arguments, see pages 3-10, filed on March 31, 2026, with respect to the rejection of claims 1-20 under 35USC103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, claims 1-20 remain rejected under the judicially created doctrine of obviousness-type double patenting. The applicants are advised to file Terminal Disclaimer to overcome the rejection.
Conclusion
8. All claims are rejected.
9.. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
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