DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 04/21/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "8" and "22" have both been used to designate “an insulating film”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 9 are rendered indefinite because they both recite the limitation of “an insulating film” in page 2 lines 3-4 and page 3 line 19, respectively. The structure of the claimed “insulating film” as shown in Figures 2-11 and the structure of the claimed “insulating film” in Figure 11 are different from one another as indicated by different reference numerals. Because these elements have different structures, they need to be referred to using different terms and clarified in the claims instead of “an insulating film” and ”an insulating film”.
Claims 2-8 depend on claim 1 and are therefore also rendered indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Oda (Japanese Patent Application Publication 2021-015885A) in view of Laforet (US Patent Application Publication 2025/0063794A1).
Regarding claim 1, Oda (Japanese Patent Application Publication 2021-015885A) teaches a semiconductor device (semiconductor device, Figure 1) including an active region (cell region, Figure 1, paragraph 0016, teaches the MOSFETs shown in these figures are formed in the cell region of the semiconductor device) in which a semiconductor switching element (IGBT, Figure 1, paragraph 0015 + 0063, teaches a semiconductor device provided with an n-channel type MOSFET having a trench gate structure having a two-layer structure...In the case of the IGBT, it is the same as the vertical MOSFET described in the above embodiment except that the conductive type of the semiconductor substrate is changed from the n type to the p type) is provided and an outer surrounding region (outer peripheral region, Figure 1, paragraph 0016, teaches the semiconductor device is provided with an outer peripheral region so as to surround the portion shown in FIG. 1, but only the MOSFET is shown here) in which a gate electrode (gate wiring 12, Figure 3, paragraph 0027, teaches the gate wiring is also electrically connected to the gate electrode layer through a connecting portion such as a W plug in the contact hole formed in the interlayer insulating film) is provided on an outer side of the active region, wherein the semiconductor switching element includes: a first conductivity type drift layer (n--type drift layer 2, Figure 2); a second conductivity type base layer (p-type body region 3, Figure 2, paragraph 0018, teaches a p-type body region having a relatively low impurity concentration is formed at a desired position on the surface layer portion of the n--type drift layer...the p-type body region is formed with the y direction as the longitudinal direction among a plurality of trench gate structures described later) provided on a side of an upper surface of the first conductivity type drift layer; a first conductivity type source layer (n-type impurity region 4, Figure 2, paragraph 0019, teaches an n-type impurity region corresponding to a source region having a higher impurity concentration than the n--type drift layer. Further, a contact trench is formed in the n-type impurity region, and the p-type body region is exposed on the bottom surface of the contact trench. Although not shown here, a p+-type contact region serving as a body contact can also be formed in an exposed portion of the p-type body region. Further, an n+-type contact region serving as a source contact can be formed on the side surface of the contact trench in the n-type impurity region) provided on a side of an upper surface of the second conductivity type base layer; a second conductivity type collector layer (n+-type semiconductor substrate 1, Figure 2, paragraph 0017 + 0063, teaches the semiconductor device according to the present embodiment is formed by using an n+-type semiconductor substrate made of a semiconductor material such as silicon having a high impurity concentration. On the surface of the n+-type semiconductor substrate, the impurity concentration than the semiconductor substrate of n+-type low concentration it has been n--type drift layer is formed...In the case of the IGBT, it is the same as the vertical MOSFET described in the above embodiment except that the conductive type of the semiconductor substrate is changed from the n-type to the p-type) provided on a side of a lower surface of the first conductivity type drift layer; an emitter electrode (upper electrode 10 or shield wiring 13, Figure 3, paragraph 0026, teaches the upper electrode is electrically connected to the n-type impurity region or the shield wiring corresponding to a source electrode are formed on the interlayer insulating film) electrically connected to the first conductivity type source layer, and a collector electrode (lower electrode 15, Figure 2, claim 1, teaches a lower electrode that is electrically connected to the high concentration layer) electrically connected to the second conductivity type collector layer, wherein a range from an upper surface of the first conductivity type source layer to a lower surface of the second conductivity type collector layer is defined as a semiconductor substrate (n+-type semiconductor substrate 1 + n--type drift layer 2 + gate trenches 5 + shield electrode 7 + insulating film 6 + p-type body region 3 + gate electrode layer 8 + n-type impurity region 4 + intermediate insulating film 9 + interlayer insulating film 11, Figure 2), the semiconductor device further includes: a plurality of trenches (gate trench 5, Figure 2, paragraph 0020, teaches a plurality of gate trenches having a longitudinal direction in one direction are formed between each p-type body region and each n-type impurity region in the surface layer portion of the n--type drift layer) passing through the semiconductor substrate from an upper surface of the semiconductor substrate to reach the first conductivity type drift layer in a depth direction, and extending from the active region toward the outer surrounding region; and an interlayer insulating film (interlayer insulating film 11, Figure 2, paragraph 0026, teaches an interlayer insulating film composed of an oxide film or the like is formed so as to cover the gate electrode layer, and an upper electrode, a gate wiring, and a shield wiring corresponding to a source electrode are formed on the interlayer insulating film) covering each of the plurality of trenches, wherein each of the plurality of trenches has a two-stage structure (paragraph 0015, teaches a trench gate structure having a two-layer structure) that a lower electrode (shield electrode 7, Figure 2, paragraph 0023 , teaches in the gate trench, a shield electrode composed of doped Poly-Si and a gate electrode layer are laminated via an insulating film to form a two-layer structure), a boundary insulating film (intermediate insulating film 9, Figure 2, paragraph 0024, teaches intermediate insulating film is formed between the shield electrode and the gate electrode layer, and the shield electrode and the gate electrode layer are insulated by the intermediate insulating film), and an upper electrode (gate electrode layer 8, Figure 2, paragraph 0024, teaches The trench gate structure is composed of the gate trench, the insulating film, the shield electrode, the gate electrode layer and the intermediate insulating film) are stacked in sequence via an insulating film (insulating film 6, Figure 2, paragraph 0024, teaches The trench gate structure is composed of the gate trench, the insulating film, the shield electrode, the gate electrode layer and the intermediate insulating film) inside each of the plurality of trenches, the lower electrode is electrically connected to the emitter electrode (Figure 3, paragraph 0027, teaches the shield wiring is also electrically connected to the shield electrode through a connection portion such as a W plug in the contact hole formed in the interlayer insulating film), the upper electrode is electrically connected to the gate electrode (Figure 3, paragraph 0027, teaches "the gate wiring is also electrically connected to the gate electrode layer through a connecting portion such as a W plug in the contact hole formed in the interlayer insulating film), an extension part of the lower electrode (connection portion 13a, Figure 3) extending to an outer side of the upper electrode further extends to the upper surface of the semiconductor substrate to cover an end portion of the upper electrode, in an outer surrounding part of each of the plurality of trenches located in the outer surrounding region in an extension direction, as claimed.
Oda (Japanese Patent Application Publication 2021-015885A) is silent to teach a width of each of the plurality of trenches is smallest in the end portion of each of the plurality of trenches.
In an analogous art, Laforet (US Patent Application Publication 2025/0063794A1) teaches a width (width w2, Figure 1C, paragraph 0041, teaches As the field plate and the field dielectric together fill the columnar trench, the field plate has a larger width in the upper portion of the trench than its width in the lower portion of the trench) of each of the plurality of trenches is smallest in the end portion of each of the plurality of trenches (trench 14 and/or field plate 21, Figure 1C), as claimed.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Oda (Japanese Patent Application Publication 2021-015885A) by making the trenches have a smaller width at an end portion as taught by Laforet (US Patent Application Publication 2025/0063794A1) thereby increasing the electric field strength and hole density at the trench end, improving the avalanche withstand voltage.
Regarding claim 2, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 1, as claimed. Oda (Japanese Patent Application Publication 2021-015885A) further teaches wherein the width of each of the plurality of trenches is smallest in a region corresponding to the extension part of the lower electrode and a part of the upper electrode in the plurality of trenches (Figure 4).
PNG
media_image1.png
620
633
media_image1.png
Greyscale
Regarding claim 3, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 1, as claimed. Laforet (US Patent Application Publication 2025/0063794A1) further teaches wherein the width of each of the plurality of trenches is gradually reduced toward a tip end of the trench end portion (paragraph 0035, teaches the columnar trench has a small or narrow circumference or width in proportion to its height/depth in the substrate).
Regarding claim 4, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 3, as claimed. Laforet (US Patent Application Publication 2025/0063794A1) further teaches wherein the width of each of the plurality of trenches is reduced in stages (paragraph 0041, teaches In cross-section, the field plate may have a T-shape or a tapered V-shape).
Regarding claim 5, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 3, as claimed. Laforet (US Patent Application Publication 2025/0063794A1) further teaches wherein a taper is provided to the trench end portion (paragraph 0041, teaches In cross-section, the field plate may have a T-shape or a tapered V-shape
Regarding claim 6, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 3, as claimed. Oda (Japanese Patent Application Publication 2021-015885A) further teaches wherein the tip end of the trench end portion is formed into a round shape (Figure 4, paragraph 0021, teaches the width of the gate trench gradually narrows toward the bottom, and the bottom is rounded).
Regarding claim 7, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 1, as claimed. Oda (Japanese Patent Application Publication 2021-015885A) further teaches wherein the width of each of the plurality of trenches is gradually reduced toward the tip end of the trench end portion from a width of a region with a largest trench width (Figure 4).
PNG
media_image2.png
540
571
media_image2.png
Greyscale
Regarding claim 8, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 7, as claimed. Oda (Japanese Patent Application Publication 2021-015885A) further teaches wherein the region with the largest trench width is included in a lifting region connecting the upper electrode to the gate electrode (Figure 4).
PNG
media_image3.png
471
504
media_image3.png
Greyscale
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) in view of Yedinak (US Patent Application Publication 2014/0264569A1).
Regarding claim 9, Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) teach the semiconductor device according to claim 1, as claimed.
Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (US Patent Application Publication 2025/0063794A1) are silent to teach wherein a cross trench is further provided to connect an area of the tip end of the trench end portion and the tip end of the trench end portion adjacent to each other in the plurality of trenches, a cross electrode is provided inside the cross trench via an insulating film, and the cross electrode is electrically connected to the emitter electrode.
In an analogous art, Yedinak (US Patent Application Publication 2014/0264569A1) teaches wherein a cross trench (trench 970G, Figure 10M) is further provided to connect an area of the tip end of the trench end portion and the tip end of the trench end portion adjacent to each other in the plurality of trenches, a cross electrode (shield electrode 930G, Figure 10M) is provided inside the cross trench via an insulating film (dielectric 970A, Figure 10M), and the cross electrode is electrically connected to the emitter electrode. Since the cross electrode is connected to the lower electrode, which is also electrically connected to the emitter electrode, the cross electrode is inturn electrically connected to the emitter electrode.
Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Oda (Japanese Patent Application Publication 2021-015885A) and Laforet (German Patent Application Publication 10-2023-121993A1) by having a cross trench and cross electrode coated in an insulating film connecting the trenches as in Yedinak (US Patent Application Publication 2014/0264569A1) thereby increasing the electric field strength at the trench end, improving the avalanche withstand voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.M.A./Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights