Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 18, 21, 24 are rejected under 35 U.S.C. l12(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 18, 21, 24 recites “the normal data and the repair data” where the scope related to said limitation is deemed indefinite. Because, in independent claim 16 and 23 clearly recite “generate normal data or repair data” i.e. it ca be either normal data or repair data but the limitation in dependent claim “the normal data and the repair data” indicate specifically both normal and repair data which is not clear and indefinite.
For the purpose of examination, it will be examined as only normal data.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (US Pub # 2021/0225423).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Moon et al. teach a memory device comprising: a base die configured to transmit transmission data that are driven to a first voltage range through a transmission line based on base data (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0066-0074, 0084-0086, 110 is base die, Voltage Vdd transmit through power line distributer 111); and a core die configured to generate core data by shifting a voltage level of the transmission data received through the transmission line to a second voltage range (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0086, Voltage / power line distributer 111 from base die provide voltage to core die through TSV).
Even though Moon et al. teach about voltage regulator (REG) but silent exclusively about shifting a voltage level. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Moon et al. where voltage regulator generates range of voltages for base die and core die which transmit first voltage and second voltage in order to reduce noise in the core die and improve reliability of data signal (see paragraph 0041).
Regarding claim 2, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the first voltage range is set between a first power and a ground voltage (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074).
Regarding claim 3, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the second voltage range is set between a second power and a ground voltage, and wherein a voltage level of the second power is higher than a voltage level of the first power (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0072).
Regarding claim 4, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the base die comprises a buffer configured to buffer the base data, and wherein the base die transmits the transmission signal through the transmission line based on a transmission enable signal and an output signal of the buffer (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0070).
Regarding claim 5, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the transmission enable signal is enabled to transmit the transmission signal through the transmission line (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0061).
Regarding claim 6, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the core die: shifts a voltage level of the transmission signal, and outputs the signal having the shifted voltage level as the core data based on a reception enable signal (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0073).
Regarding claim 7, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Moon et al. further teach, wherein the reception enable signal is enabled to receive the transmission signal from the core die through the transmission line (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074).
Regarding independent claim 8, Moon et al. teach a memory device comprising: a base die configured to shift a level of base data that are driven to a first voltage range to a second voltage range and configured to transmit transmission data through a transmission line based on a transmission enable signal (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0066-0074, 0084-0086, 110 is base die, Voltage Vdd transmit through power line distributer 111); and a core die configured to generate core data based on the transmission data and a reception enable signal range (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0086, Voltage / power line distributer 111 from base die provide voltage to core die through TSV).
Even though Moon et al. teach about voltage regulator (REG) but silent exclusively about shift a level. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Moon et al. where voltage regulator generates range of voltages for base die and core die which transmit first voltage and second voltage in order to reduce noise in the core die and improve reliability of data signal (see paragraph 0041).
Regarding claim 9, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Moon et al. further teach, wherein the first voltage range is set between a first power and a ground voltage, and wherein the second voltage range is set between a second power and the ground voltage, and wherein a voltage level of the second power is higher than a voltage level of the first power (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062).
Regarding claim 10, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Moon et al. further teach, wherein the base die comprises: a buffer configured to buffer the base data in the first voltage range; a level shifter configured to output an output signal of the buffer by shifting a voltage level of the output signal to the second voltage range; and a driving circuit configured to output the transmission data through the transmission line by driving the transmission data based on the output signal of the level shifter and the transmission enable signal (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0086).
Regarding claim 11, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Moon et al. further teach, wherein the transmission enable signal is enabled to transmit the transmission signal through the transmission line (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069).
Regarding claim 12, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Moon et al. further teach
, wherein the level shifter is implemented by using a plurality of multiple MOS transistors, and wherein an insulating layer of some MOS transistors that operate in the second voltage range, among the plurality of MOS transistors, are set to be thicker than an insulating layer of the remaining MOS transistors (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0060).
Regarding claim 13, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Moon et al. further teach, wherein the driving circuit is implemented by using a plurality of multiple MOS transistors, and wherein an insulating layer of some MOS transistors that operate in the second voltage range, among the plurality of MOS transistors, are set to be thicker than an insulating layer of the remaining MOS transistors (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054).
Regarding claim 14, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 8 on which this claim depends.
Moon et al. further teach, wherein the base die comprises: a buffer configured to buffer the base data in the first voltage range; a level shifter configured to output an output signal of the buffer by shifting a voltage level of the output signal to the second voltage range; a duty ratio adjustment circuit configured to output the output signal of the level shifter by adjusting a duty ratio of the output signal; and a driving circuit configured to output the transmission data through the transmission line by driving the transmission data based on the output signal of the duty ratio adjustment circuit and the transmission enable signal (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0085).
Regarding claim 15, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Moon et al. further teach, wherein each of the level shifter, the duty ratio adjustment circuit, and the driving circuit is implemented by using a plurality of MOS transistors, and wherein an insulating layer of some MOS transistors that operate in the second voltage range, among the plurality of MOS transistors, are set to be thicker than an insulating layer of the remaining MOS transistors (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0086).
Regarding independent claim 16, Moon et al. teach a memory device comprising: a core die configured to generate transmission data in a second voltage range by buffering core data and configured to transmit the transmission data to a transmission line range (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0086, Voltage / power line distributer 111 from base die provide voltage to core die through TSV); and a base die configured to buffer the transmission data, configured to shift a voltage level of the transmission data to a first voltage range (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0066-0074, 0084-0086, 110 is base die, Voltage Vdd transmit through power line distributer 111), and configured to generate normal data or repair data depending on whether the transmission data have been repaired.
Even though Moon et al. teach about voltage regulator (REG) but silent exclusively about shift a voltage level. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Moon et al. where voltage regulator generates range of voltages for base die and core die which transmit first voltage and second voltage in order to reduce noise in the core die and improve reliability of data signal (see paragraph 0041).
Regarding claim 17, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Moon et al. further teach, wherein the first voltage range is set between a first power and a ground voltage, and wherein the second voltage range is set between a second power and the ground voltage, and wherein a voltage level of the second power is higher than a voltage level of the first power (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074).
Regarding claim 18, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Moon et al. further teach, wherein the base die comprises: a data reception circuit configured to buffer the transmission data in the second voltage range based on a reception enable signal; a level shifter configured to shift a voltage level of an output signal of a buffer to the first voltage range; and a data selection generation circuit configured to selectively generate one of the normal data and the repair data from an output signal of the level shifter based on the reception enable signal and a repair enable signal (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084).
Regarding claim 19, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Moon et al. further teach, wherein the reception enable signal is enabled to receive the transmission data in a state in which an error has not occurred in the transmission data (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062).
Regarding claim 20, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Moon et al. further teach, wherein the repair enable signal is enabled to receive the transmission data in a state in which an error has occurred in the transmission data (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0060).
Regarding claim 21, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Moon et al. further teach, wherein the data selection generation circuit: generates the normal data from the output signal of the level shifter when the reception enable signal is enabled, and generates the repair data from the output signal of the level shifter when the repair enable signal is enabled (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062).
Regarding claim 22, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 20 on which this claim depends.
Moon et al. further teach, wherein each of the data reception circuit, the level shifter, and the data selection generation circuit is implemented by using a plurality of MOS transistors, and wherein an insulating layer of some MOS transistors that operate in the second voltage range, among the plurality of MOS transistors, are set to be thicker than an insulating layer of the remaining MOS transistors (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074).
Regarding independent claim 23, Moon et al. teach a memory device comprising: a core die configured to generate transmission data by buffering core data in a second voltage range and configured to transmit the transmission data to a transmission line range (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0086, Voltage / power line distributer 111 from base die provide voltage to core die through TSV); and a base die configured to shift a voltage level of the transmission data to a first voltage range and configured to generate normal data or repair data depending on whether the transmission data have been repaired (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0066-0074, 0084-0086, 110 is base die, Voltage Vdd transmit through power line distributer 111).
Even though Moon et al. teach about voltage regulator (REG) but silent exclusively about shift a voltage level. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Moon et al. where voltage regulator generates range of voltages for base die and core die which transmit first voltage and second voltage in order to reduce noise in the core die and improve reliability of data signal (see paragraph 0041).
Regarding claim 24, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 23 on which this claim depends.
Moon et al. further teach, wherein the base die comprises: a level shifter configured to shift the voltage level of the transmission data to the first voltage range; and a data selection generation circuit configured to selectively generate one of normal data and repair data from an output signal of the level shifter based on a reception enable signal and a repair enable signal (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069).
Regarding claim 25, Moon et al. teach all claimed subject matter as applied in prior rejection of claim 24 on which this claim depends.
Moon et al. further teach, wherein each of the level shifter and the data selection generation circuit is implemented by using a plurality of MOS transistors, and wherein an insulating layer of some MOS transistors that operate in the second voltage range, among the plurality of MOS transistors, are set to be thicker than an insulating layer of the remaining MOS transistors (see Fig. 1-2, 6 and paragraph 0024-0031, 0033-0035, 0037-0039, 0043-0054, 0059-0062, 0069-0074, 0084-0085).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824