Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated April 2, 2026, claims 1-22, 24 and 26 are active in
this application.
Claim Objections
Claims 4-7, 11-14 and 18-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuan et al. [US Patent # 8,456,911].
With respect to claim 1, Yuan et al. disclose an electrical parameter adjustment [“…the indication of the program/erase cycles performed in order to dynamically and automatically calculate (or adjust) the current read pass voltage (Vreadc).” – fig. 12 and col. 17, lines 25-35] method for a rewritable non-volatile memory module [figs. 1-6], wherein the rewritable non-volatile memory module comprises a plurality of physical units [fig. 5], the electrical parameter adjustment method comprising: detecting a status of the rewritable non-volatile memory module [step 644 involve accessing the read pass voltage optimized for the memory is a detection step]; in response to the status of the rewritable non-volatile memory module meeting a first condition, sending a single-state read command [step 646], wherein the single-state read command instructs reading a first physical unit among the physical units based on a specific voltage [step 650], and the specific voltage is a read pass voltage corresponding to the first physical unit [Vcgr – step 650]; and adjusting at least one electrical parameter of the rewritable non-volatile memory module [loop of steps 650-654] according to a read result of the single-state read command [step 656].
With respect to claim 2, Yuan et al. disclose the step of detecting the status of the rewritable non-volatile memory module comprises: obtaining a wear evaluation value, wherein the wear evaluation value reflects a wear status of the rewritable non-volatile memory module; and in response to the wear evaluation value reaching a first threshold value, judging that the status of the rewritable non-volatile memory module meets the first condition. The accessing steps of fig. 12 rely on the status of the memory cells, in terms of wear data [“…Once the non-volatile storage system is manufactured and configured, it may be used to program and read data. Step 550 is optionally performed as part of a process to program data. In one example implementation, memory cells are pre-programmed in order to maintain even wear on the memory cells (step 550).” – col. 10, lines 1-15].
With respect to claim 3, Yuan et al. disclose the read pass voltage corresponding to the first physical unit is configured to be applied to the first physical unit during a period of executing a read operation on a second physical unit among the physical units to conduct a plurality of memory cells in the first physical unit. Read pass voltages are applied to selected cells and neighboring cells [wordlines] – see steps 650, 652 and 654.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuan et al. [US Patent # 8,456,911].
With respect to claim 8, Yuan et al. disclose a memory storage device [figs. 1-6], comprising: a connection interface unit [244], configured to couple to a host system [via 232]; a rewritable non-volatile memory module [200]; and a memory control circuit unit [220], coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units [within 200], and the memory control circuit unit is configured to: detect a status of the rewritable non-volatile memory module [step 644 involve accessing the read pass voltage optimized for the memory is a detection step]; in response to the status of the rewritable non-volatile memory module meeting a first condition, send a single-state read command [step 646], wherein the single-state read command instructs reading a first physical unit among the physical units based on a specific voltage [step 650], and the specific voltage is a read pass voltage corresponding to the first physical unit [Vcgr – step 650]; and adjust at least one electrical parameter of the rewritable non-volatile memory module [loop of steps 650-654] according to a read result of the single-state read command [step 656].
With respect to claim 9, Yuan et al. disclose the operation of the memory control circuit unit detecting the status of the rewritable non-volatile memory module comprises: obtaining a wear evaluation value, wherein the wear evaluation value reflects a wear status of the rewritable non-volatile memory module; and in response to the wear evaluation value reaching a first threshold value, judging that the status of the rewritable non-volatile memory module meets the first condition. The accessing steps of fig. 12 rely on the status of the memory cells, in terms of wear data [“…Once the non-volatile storage system is manufactured and configured, it may be used to program and read data. Step 550 is optionally performed as part of a process to program data. In one example implementation, memory cells are pre-programmed in order to maintain even wear on the memory cells (step 550).” – col. 10, lines 1-15].
With respect to claim 10, Yuan et al. disclose the read pass voltage corresponding to the first physical unit is configured to be applied to the first physical unit during a period of executing a read operation on a second physical unit among the physical units to conduct a plurality of memory cells in the first physical unit. Read pass voltages are applied to selected cells and neighboring cells [wordlines] – see steps 650, 652 and 654.
Claim(s) 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuan et al. [US Patent # 8,456,911].
With respect to claim 15, Yuan et al. disclose a memory control circuit unit [220], configured to control a rewritable non-volatile memory module [200], wherein the rewritable non-volatile memory module comprises a plurality of physical units [within 200], the memory control circuit unit comprising: a host interface [244], configured to couple to a host system [via 232]; a memory interface [242a], configured to couple to the rewritable non-volatile memory module; and a memory management circuit [226/224/222], coupled to the host interface and the memory interface, wherein the memory management circuit is configured to: detect a status of the rewritable non-volatile memory module [step 644 involve accessing the read pass voltage optimized for the memory is a detection step]; in response to the status of the rewritable non-volatile memory module meeting a first condition, send a single-state read command [step 646], wherein the single-state read command instructs reading a first physical unit among the physical units based on a specific voltage [step 650], and the specific voltage is a read pass voltage corresponding to the first physical unit [Vcgr – step 650]; and adjust at least one electrical parameter of the rewritable non-volatile memory module [loop of steps 650-654] according to a read result of the single-state read command [step 656].
With respect to claim 16, Yuan et al. disclose the operation of the memory management circuit detecting the status of the rewritable non-volatile memory module comprises: obtaining a wear evaluation value, wherein the wear evaluation value reflects a wear status of the rewritable non-volatile memory module; and in response to the wear evaluation value reaching a first threshold value, judging that the status of the rewritable non-volatile memory module meets the first condition. The accessing steps of fig. 12 rely on the status of the memory cells, in terms of wear data [“…Once the non-volatile storage system is manufactured and configured, it may be used to program and read data. Step 550 is optionally performed as part of a process to program data. In one example implementation, memory cells are pre-programmed in order to maintain even wear on the memory cells (step 550).” – col. 10, lines 1-15].
With respect to claim 17, Yuan et al. disclose the read pass voltage corresponding to the first physical unit is configured to be applied to the first physical unit during a period of executing a read operation on a second physical unit among the physical units to conduct a plurality of memory cells in the first physical unit. Read pass voltages are applied to selected cells and neighboring cells [wordlines] – see steps 650, 652 and 654.
Remarks
Applicant's arguments filed April 2, 2026 have been fully considered but they are not
persuasive.
Applicant argued “that the cited reference fails to teach or suggest the feature "sending a single-state read command, wherein the single-state read command instructs reading a first physical unit among the physical units based on a specific voltage, and the specific voltage is a read pass voltage corresponding to the first physical unit; and adjusting at least one electrical parameter of the rewritable non-volatile memory module according to a read result of the single-state read command" as recited in claim 1.” Additionally, Applicant indicated that “Yuan is directed to optimizing a current read pass voltage (Vreadc) prior to a read operation. Vreadc is dynamically calculated based on voltages optimized for fresh and cycled memory and program/erase cycle information. Yuan's focus is therefore on determining an appropriate voltage before reading, not on adjusting any parameter based on a read result.” The Examiner respectfully disagrees.
Yuan teaches all claimed recitations as follows:
"sending a single-state read command": Matches Yuan’s method as optimizing a voltage prior to a read operation implies a preparatory action.
"instructs reading a first physical unit": Matches as Yuan focuses on determining the optimal voltage for specific memory cells.
"based on a specific voltage": Matches Yuan’s method as the optimized Vreadc is determined by P/E cycle information.
"voltage is a read pass voltage": Matches Yuan’s method as Vreadc is explicitly defined as the read pass voltage for the unit.
"adjusting at least one electrical parameter... according to a read result": Matches, as Yuan method of dynamically adjusts Vreadc (the parameter) based on the unit's state (the result).
Additionally, in the claim, the recitation of "...adjusting at least one electrical parameter of the
rewritable non-volatile memory module according to a read result of the single-state read command." Is supported by Yuan’s method. The method finds the best RRV [Read Reference Voltage] by multiple read-retry operations during the first read operation and records it. The "read result" (data read during initial read-retry operations) is used to determine and adjust the Read Reference Voltage (an electrical parameter) for future reads.
Further, the application's "single-state read command" aligns with Yuan's approach of analyzing the memory cell state to determine an optimal Vreadc. Ref Yuan explicitly states Vreadc is dynamically calculated, adjusting the read pass voltage based on the P/E cycle history. By adjusting the read pass voltage based on the P/E cycle information, Yuan adjusts an electrical parameter Vreadc in response to the characteristics of the physical unit.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
Allowable Subject Matter
Claims 22, 24 and 26 are allowable over the prior art of records.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 4: The electrical parameter adjustment method according to claim 1, wherein the at least one electrical parameter comprises at least one of a programming voltage corresponding to the first physical unit, a programming pass voltage corresponding to the first physical unit, an erase voltage corresponding to the first physical unit, an erase verification voltage corresponding to the first physical unit, and the read pass voltage corresponding to the first physical unit.
-with respect to claim 6: The electrical parameter adjustment method according to claim 1, wherein the step of adjusting the at least one electrical parameter of the rewritable non-volatile memory module according to the read result of the single-state read command comprises: in response to a total number of a plurality of target bits read through the single-state read command reaching a second threshold value, adjusting the at least one electrical parameter of the rewritable non-volatile memory module.
-with respect to claim 11: The memory storage device according to claim 8, wherein the at least one electrical parameter comprises at least one of a programming voltage corresponding to the first physical unit, a programming pass voltage corresponding to the first physical unit, an erase voltage corresponding to the first physical unit, an erase verification voltage corresponding to the first physical unit, and the read pass voltage corresponding to the first physical unit.
-with respect to claim 13: The memory storage device according to claim 8, wherein the operation of the memory control circuit unit adjusting the at least one electrical parameter of the rewritable non-volatile memory module according to the read result of the single-state read command comprises: in response to a total number of a plurality of target bits read through the single-state read command reaching a second threshold value, adjusting the at least one electrical parameter of the rewritable non-volatile memory module.
-with respect to claim 18: The memory control circuit unit according to claim 15, wherein the at least one electrical parameter comprises at least one of a programming voltage corresponding to the first physical unit, a programming pass voltage corresponding to the first physical unit, an erase voltage corresponding to the first physical unit, an erase verification voltage corresponding to the first physical unit, and the read pass voltage corresponding to the first physical unit.
-with respect to claim 20. The memory control circuit unit according to claim 15, wherein the operation of the memory management circuit adjusting the at least one electrical parameter of the rewritable non-volatile memory module according to the read result of the single-state read command comprises: in response to a total number of a plurality of target bits read through the single-state read command reaching a second threshold value, adjusting the at least one electrical parameter of the rewritable non-volatile memory module.
-with respect to claim 22, wherein the step of detecting the status of the rewritable non-volatile memory module comprises: obtaining a wear evaluation value, wherein the wear evaluation value reflects a wear status of the rewritable non-volatile memory module; and in response to the wear evaluation value reaching a first threshold value, judging that the status of the rewritable non-volatile memory module meets the first condition.
-with respect to claim 24, wherein the operation of the memory control circuit unit detecting the status of the rewritable non-volatile memory module comprises: obtaining a wear evaluation value, wherein the wear evaluation value reflects a wear status of the rewritable non-volatile memory module; and in response to the wear evaluation value reaching a first threshold value, judging that the status of the rewritable non-volatile memory module meets the first condition.
-with respect to claim 26, wherein the operation of the memory management circuit detecting the status of the rewritable non-volatile memory module comprises: obtaining a wear evaluation value, wherein the wear evaluation value reflects a wear status of the rewritable non-volatile memory module; and in response to the wear evaluation value reaching a first threshold value, judging that the status of the rewritable non-volatile memory module meets the first condition.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 May 2, 2026
Prosecution Insights