DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7, 9-11, 14, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20230089578 (Rajashekhar et al).
Concerning claim 1, Rajashekhar discloses a semiconductor device (Figs. 7A and 16A-16H), comprising:
PNG
media_image1.png
366
279
media_image1.png
Greyscale
a memory array (100) of memory cells (55) (Fig. 7A); and bit lines (118) coupled to the memory array (Fig. 16H), wherein adjacent bit lines of the bit lines are separated by an isolating region (130) along a first direction (hd1), the isolating region extending along a second direction perpendicular to the first direction (Fig. 16H), the isolating region comprising an air gap (119), wherein, along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines (Annotated Fig. 16H above shows that the air gap 119 terminates above the termination of the bit line 118).
Continuing to claim 4, Rajashekhar discloses wherein the air gap is surrounded by an isolating material (Fig. 16H).
Considering claim 7, Rajashekhar discloses wherein, along the second direction, the end of the air gap is away the adjacent end of the bit line of the adjacent bit lines by a height, and wherein a ratio of the height to a width of the isolation region along the first direction is in a range from about 0 to about 0.8 (Fig. 16H).
Referring to claim 9, Rajashekhar discloses wherein the air gap comprises a first portion and a second portion that are arranged along the second direction, and wherein a width of the air gap along the first direction in the first portion is smaller than a width of the air gap along the first direction in the second portion (Fig. 16H).
Regarding claim 10, Rajashekhar discloses wherein the width of the air gap along the first direction gradually decreases towards the end of the air gap in the first portion of the air gap (Fig. 16H).
Pertaining to claim 11, Rajashekhar discloses wherein a ratio of a maximum width of the air gap along the first direction to a width of the isolation region along the first direction is greater than 0.6 (Fig. 16H).
As to claim 14, Rajashekhar discloses a method (Figs. 16A-16H), comprising:
PNG
media_image1.png
366
279
media_image1.png
Greyscale
forming bit lines (118) separated by a dielectric material (122) (Fig. 16E); etching the dielectric material between adjacent bit lines of the bit lines to form a trench between the adjacent bit lines along a first direction (hd1) (Figs. 16E-16F and [0145]-[0148]); and forming an isolating region (130) in the trench between the adjacent bit lines (Fig. 16H), the isolating region extending along a second direction perpendicular to the first direction (Fig. 16H), wherein the isolating region comprises an air gap (119) surrounded by an isolating material, and, along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines (Annotated Fig. 16H above shows that the air gap 119 terminates above the termination of the bit line 118).
Concerning claim 16, Rajashekhar discloses wherein the isolating region between the adjacent bit lines is formed using plasma enhanced chemical vapor deposition (PECVD) ([0151]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230089578 (Rajashekhar et al) in view of US 20230098062 (Sukekawa).
Continuing to claims 2 and 18 (with these claims being similar in scope), Rajashekhar discloses forming a memory cell (Figs. 16A-16H).
Rajashekhar does not disclose wherein a memory cell of the memory cells comprises a transistor and a capacitor, the transistor comprising a transistor body extending along the second direction, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, and wherein the first terminal of the transistor is coupled to the capacitor, and the second terminal of the transistor is coupled to a corresponding bit line of the bit lines. However, Sukekawa discloses an apparatus with air gaps formed between adjacent bit lines (Fig. 10C) whose memory cell configuration in comprises a transistor and a capacitor, the transistor comprising a transistor body extending along the second direction, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, and wherein the first terminal of the transistor is coupled to the capacitor, and the second terminal of the transistor is coupled to a corresponding bit line of the bit lines (Claim 8). Sukekawa discloses that such configuration reduce the planar area of the memory cell, thereby increasing the memory capacity ([0001]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus configuration of Rajashekhar to include the memory cells configuration that comprises a transistor and a capacitor, the transistor comprising a transistor body extending along the second direction, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, and wherein the first terminal of the transistor is coupled to the capacitor, and the second terminal of the transistor is coupled to a corresponding bit line of the bit lines in order to reduce the planar area od the memory cell and increase the memory capacity.
Continuing to claims 3 and 19 (with these claims being similar in scope), Rajashekhar in view of Sukekawa discloses wherein, along the second direction, a distance between the end of the air gap and an end of the gate structure is greater than a distance between the adjacent end of the bit line and the end of the gate structure (Sukekawa Fig. 10C).
Claim(s) 5, 6, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230089578 (Rajashekhar et al) in view of US 20160163559 (Ryan).
Considering claim 5, Rajashekhar discloses wherein the isolating material comprises a . . . dielectric material ([0151], it is noted that one of the materials of the dielectric layer is disclosed as being an organosilicate glass which the examiner is relying on for rejection purposes).
Rajashekhar does not explicitly disclose that the organosilicate glass is a low-k porous dielectric material. However, Ryan discloses the suitable use of an organosilicate glass as an isolation layer that is formed by PECVD with a porous linkage material ([0035]) to form a low-k dielectric layer with a dielectric of 2.7 to 3 ([0036]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use an organosilicate glass as formed by Ryan in order to obtain a low-k porous dielectric material suitable for isolation structures.
Referring to claim 6, Rajashekhar in view of Ryan discloses wherein the low-k porous dielectric material has a dielectric constant in a range from about 1.5 to about 3.5 (Ryan [0036]).
Regarding claim 15, Rajashekhar discloses forming the isolation region using PECVD ([0151], it is noted that one of the materials of the dielectric layer is disclosed as being an organosilicate glass which the examiner is relying on for rejection purposes).
Rajashekhar does not explicitly disclose the materials for use in the PECVD and therefore does not disclose wherein forming the isolating region in the trench between the adjacent bit lines comprises: introducing a gas mixture of a porous linkage material in vapor phase and oxygen gas into a reaction chamber. However, Ryan discloses the suitable use of an organosilicate glass as an isolation layer that is formed by PECVD with a porous linkage material ([0035]) to form a low-k dielectric layer with a dielectric of 2.7 to 3 ([0036]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the precursors disclosed by Ryan to form an organosilicate glass in order to obtain a low-k porous dielectric material suitable for isolation structures.
Claim(s) 8, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230089578 (Rajashekhar et al) in view of US 20240008261 (Chung).
Pertaining to claims 8, 12, and 13, Rajashekhar discloses forming the air gaps in the isolating material (Fig.16H).
Rajashekhar does not disclose wherein the height is in a range from about 3 nm to about 10 nm, wherein a ratio of a height of the air gap along the second direction to a width of the isolating region along the first direction is in a range from about 2 to about 5, or wherein an aspect ratio of the air gap between a height of the air gap along the second direction and a width of the air gap is greater than or equal to 3. However, Chung discloses a memory structure (Fig. 25) that includes an air gap (AG) between adjacent bit lines (16) and wherein the height is in a range from about 3 nm to about 10 nm ([0053]), wherein a ratio of a height of the air gap along the second direction to a width of the isolating region along the first direction is in a range from about 2 to about 5 ([0060]), or wherein an aspect ratio of the air gap between a height of the air gap along the second direction and a width of the air gap is greater than or equal to 3 ([0060]). Chung discloses that the configuration has the advantage of minimizing an undesired parasitic effect ([0085]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the dimensions of the air gap of Rajashekhar in view of Chung in order to minimize and undesired parasitic effect.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230089578 (Rajashekhar et al) in view of US 20160163559 (Ryan) as applied to claim 15 above, and further in view of US 9653475 (Yashimizu et al).
As to claim 17, Rajashekhar in view of Ryan discloses wherein forming the isolating region in the trench between the adjacent bit lines comprises: controlling a size of the air gap (Rajashekhar Fig. 16H and [0152]) .
Rajashekhar in view of Ryan does not disclose wherein forming the isolating region in the trench between the adjacent bit lines comprises: controlling a size of the air gap by adjusting a concentration of the porous linkage material. However, Yashimizu discloses a method of controlling the size of an air gap formed in dielectric structure by the concentration (col. 6 lines 16-40). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to control the size of the air gap formed in Rajashekhar in view of Ryan by manipulation of the concentration of the porous linkage material because Yashimizu discloses that such materials/composition is known to be suitable for formation of tailor sized air gaps.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230098062 (Sukekawa) in view of US 20230089578 (Rajashekhar et al).
Concerning claim 20, Sukekawa discloses a system, comprising: a memory device configured to store data (Fig. 10C and [0047]), the memory device comprising: a memory array of memory cells ([0041]), and bit lines (30) coupled to the memory array ([0047] and claim 8), wherein adjacent bit lines of the bit lines are separated by an isolating region (34) ([0032]) along a first direction, the isolating region extending along a second direction perpendicular to the first direction (Fig. 10C), the isolating region comprising an air gap (36) ([0032]), . . .and a memory controller (coupled to the memory device and configured to operate the memory device ([0047]).
Sukekawa does not disclose wherein, along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines.
PNG
media_image1.png
366
279
media_image1.png
Greyscale
However, Rajashekhar discloses a memory device configuration (Fig. 16H) in which an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines (Annotated Fig. 16H above shows that the air gap 119 terminates above the termination of the bit line 118). Rajashekhar discloses that such configuration of the reentrant vertical cross-sectional profiles are also conducive to formation of larger air gaps 119 between the bit lines 118 which reduces the bit line RC delay ([0206]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of the air gaps formed in the isolating region such that an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines as disclosed by Rajashekhar in order to reduce the bit line RC delay.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230064578 discloses a memory device configuration where the air gaps are formed between adjacent bit lines and within the vertical boundaries of the bit lines (Fig. 1A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/VALERIE N NEWTON/ Examiner, Art Unit 2897 09/25/26
Prosecution Insights