DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US pub 20140209979) in combination with Lutgen et al. (US pat 9773896) and Koo et al. (US pub 20110279146).
With respect to claim 1, Lau et al. teach a structure comprising (see figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2):
a barrier layer (buffer 1) including one of GaAs and InGaAs;
wherein the barrier layer is between a substrate (n type silicon (100) substrate) and a channel layer (undoped Ga0.47In0.52As, channel).
Lau et al. teach the barrier layer having a dopant concentration but fail to the dopant concentration is about 1017 cm-3.
Lutgen et al. teach doping a barrier layer with a dopant having a concentration of about 1017 cm-3. See col. 5, lines 5-20.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Lutgen et al. into the device of Lau et al to achieve adjustment of the threshold voltage without loss in electrical properties. See col. 5, lines 5-20.
Further with respect to claim 1, how the dopant is introduced or doped into the barrier layer has not given patentable weight since claim is directed to the device.
With respect to claim 2, Lau et al. fail to teach the channel layer includes an InAs layer sandwiched between 2 layers with different composition than InAs.
Koo et al. teach a channel comprises of an InAs sandwiched between Ga layers. See para 004.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching Koo et al. into the device of Lau et al. to achieve high electron mobility. See para 0040.
With respect to claim 3, Lau et al. teach the channel layer is disposed within a transistor. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2.
With respect to claim 4, Lau et al. in combination with Lutgen et al. teach the barrier layer is P-type or N-type. See col. 5, lines 5-20 of Lutgen e tal.
With respect to claim 5, Lau et al. teach the prelayer includes arsenic. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2.
Claims 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US pub 20140209979) in combination with Lutgen et al. (US pat 9773896) and Koo et al. (US pub 20110279146).
With respect to claim 6, Lau et al. teach a structure comprising (see figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2):
a barrier layer (buffer 1);
wherein the barrier layer is between a substrate (n type silicon (100) substrate) and a channel layer (undoped Ga0.47In0.52As, channel).
Lau et al. teach the barrier layer having a dopant concentration but fail to the dopant concentration is about 1017 cm-3.
Lutgen et al. teach doping a barrier layer with a dopant having a concentration of about 1017 cm-3. See col. 5, lines 5-20.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Lutgen et al. into the device of Lau et al to achieve adjustment of the threshold voltage without loss in electrical properties. See col. 5, lines 5-20.
With respect to claim 7, Lau et al. fail to teach the channel layer includes an InAs layer sandwiched between 2 layers with different composition than InAs.
Koo et al. teach a channel comprises of an InAs sandwiched between Ga layers. See para 004.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching Koo et al. into the device of Lau et al. to achieve high electron mobility. See para 0040.
With respect to claim 8, Lau et al. teach the channel layer includes AlSb or III-V material. See para 0031.
With respect to claim 9, Lau et al. teach the channel layer includes AlGaSb or III-V material. See para 0031.
With respect to claim 10, Lau et al. teach the channel layer includes AlInSb or III-V material. See para 0031.
With respect to claim 11, Lau et al. teach the channel layer includes InAs or III-V material. See para 0031.
Claims 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (US pub 20140209979) in combination with Lutgen et al. (US pat 9773896) and Koo et al. (US pub 20110279146).
With respect to claim 12, Lau et al. teach a structure comprising (see figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2):
a barrier layer (buffer 1); and
a channel layer including a heterostructure comprising InAs (see para 0031);
wherein the barrier layer is between a substrate (n type silicon (100) substrate) and the channel layer.
Lau et al. teach the barrier layer having a dopant concentration but fail to the dopant concentration is about 1017 cm-3.
Lutgen et al. teach doping a barrier layer with a dopant having a concentration of about 1017 cm-3. See col. 5, lines 5-20.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Lutgen et al. into the device of Lau et al to achieve adjustment of the threshold voltage without loss in electrical properties. See col. 5, lines 5-20.
Further with respect to claim 12, how the dopant is introduced or doped into the barrier layer has not given patentable weight since claim is directed to the device.
With respect to claim 13, Lau et al. fail to teach the channel layer includes an InAs layer sandwiched between 2 layers with different composition than InAs.
Koo et al. teach a channel comprises of an InAs sandwiched between Ga layers. See para 004.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching Koo et al. into the device of Lau et al. to achieve high electron mobility. See para 0040.
With respect to claim 14, Lau et al. teach the channel layer includes AlSb or III-V material. See para 0031.
With respect to claim 15, Lau et al. teach the channel layer includes AlGaSb or III-V material. See para 0031.
With respect to claim 16, Lau et al. teach the channel layer includes AlInSb or III-V material. See para 0031.
With respect to claim 17, Lau et al. teach the channel layer includes InAs or III-V material. See para 0031.
With respect to claim 18, Lau et al. teach the channel layer is disposed within a transistor. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2.
With respect to claim 19, Lau et al. in combination with Lutgen et al. teach the barrier layer is P-type or N-type. See col. 5, lines 5-20 of Lutgen e tal.
With respect to claim 20, Lau et al. teach the prelayer includes arsenic. See figs. 1-2 and associated text, para 0005, 0006, 0007, claims and tables 1 and 2.
Response to Arguments
Applicant's arguments filed 8/15/25 have been fully considered but they are not persuasive. See below.
In response to the applicant’s argument that Lau et al of the primary reference ‘979 teach away from doping the barrier layer with a dopant as suggested by the combination of Lau et al. and Lutgen et al. in the pending rejection. However, the combination of Lau et al. and Lutgen et al. merely teach doping the barrier layer with a dopant to achieve the benefit of controlling of the threshold-voltage because “a prior art reference is evaluated by what it suggests to one versed in the art, rather than by its specific disclosure. In re Bozek, 163 USPQ 545 (CCPA 1969)”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/ Primary Examiner, Art Unit 2897