DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/ patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of US 11,803,489. Although the claims at issue are not identical, they are not patentably distinct from each other because it is clear from the language of the claims that the invention set forth in claims 2-21 can be practiced by the invention set forth in claims 1-17 of US 11,803,489.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 11,829,308 . Although the claims at issue are not identical, they are not patentably distinct from each other because it is clear from the language of the claims that the invention set forth in claims 1-20 can be practiced by the invention set forth in claims 1-20 of US 11,829,308.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US 12,072,817. Although the claims at issue are not identical, they are not patentably distinct from each other because it is clear from the language of the claims that the invention set forth in claims 1-20 can be practiced by the invention set forth in claims 1-20 of US 12,072,817.
Regarding claim 2, US 11,803,489 teaches a method of operation in a flash memory controller to control a flash memory device, the method comprising: at startup of the flash memory device, sending, to a receiver circuit of the flash memory device, signals having a first voltage swing at a first signaling frequency, wherein the flash memory device is to initialize an internal reference voltage to a default voltage for the receiver circuit; and sending a first command that specifies calibration of the flash memory device during a calibration mode, wherein the calibration mode is used to calibrate the flash memory device to operate at a second signaling frequency and receive signals having a second voltage swing, wherein the second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency. (claim 1).
Regarding claim 2, 11,829,308 teaches a method of operation in a flash memory controller to control a flash memory device, the method comprising: at startup of the flash memory device, sending, to a receiver circuit of the flash memory device, signals having a first voltage swing at a first signaling frequency, wherein the flash memory device is to initialize an internal reference voltage to a default voltage for the receiver circuit; and sending a first command that specifies calibration of the flash memory device during a calibration mode, wherein the calibration mode is used to calibrate the flash memory device to operate at a second signaling frequency and receive signals having a second voltage swing, wherein the second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency(claim 1).
Regarding claim 2, 12,072,817 teaches a method of operation in a flash memory controller to control a flash memory device, the method comprising: at startup of the flash memory device, sending, to a receiver circuit of the flash memory device, signals having a first voltage swing at a first signaling frequency, wherein the flash memory device is to initialize an internal reference voltage to a default voltage for the receiver circuit; and sending a first command that specifies calibration of the flash memory device during a calibration mode, wherein the calibration mode is used to calibrate the flash memory device to operate at a second signaling frequency and receive signals having a second voltage swing, wherein the second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency(claim 1).
Claims 3-21 are also taught by claims 1-17 of US 11,803,489.
Claims 3-21 are also taught by claims 1-20 of US 11,829,308.
Claims 3-21 are also taught by claims 1-20 of US 12,072,817.
Conclusion
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/NIMESH G PATEL/Primary Examiner, Art Unit 2176
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