Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SOLID-STATE IMAGING ELEMENT INCLUDING CONVERSION EFFICIENCY SWITCHING SWITCH AND A CHARGE HOLDING UNIT INCLUDING A WIRING CAPACITY AND ELECTRONIC DEVICE INCLUDING THE SAME
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sano; Takuya et al. (WO 2016/163240; note: US 2018/0098007 is used as the English translation; hereinafter Sano).
Note: The citations below are directed towards the Third Configuration Example (Figs 10-12; ¶ [0059-65]) of the disclosure, in particular. Because only relevant differences to other disclosed configuration examples are described for the Third Configuration Example, citations refer to other examples throughout the disclosure as needed. The Examiner considers that it would be clear to a person of ordinary skill in the art that the cited features are included in each configuration example, even if not labeled or re-described in each.
Further, the Examiner considers that it would have been obvious to a person of ordinary skill in the art to combine the equivalent circuit diagrams (Figs 5,7) directed towards one configuration example with the additional exemplary figures and associated descriptions in the manner described below, without further motivation beyond interpretation of the disclosure. Alternately, or additionally, such combination may be considered as combining prior art elements (all within Sano’s disclosure) according to known methods to yield predicable results and/or as simple substitutions of one known element (of one configuration example of Sano) for another (another configuration example) to obtain predictable results. Each of the cited exemplary configurations is directed toward providing a switchable additional capacitance (in addition to a {floating} diffusion capacitance) to enable a switchable conversion efficiency. (¶ [0020-23, 0082, 0083(2)-0083(4)]). See MPEP 2143.I.A and 2143.I.B.
Annotated copies of some of the cited figures are included below:
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Regarding claim 1, Sano discloses a solid-state imaging element (CMOS image sensor; ¶ [0046]), comprising:
a pixel, (one of eight shown in Fig 10 as described in paragraphs [0019, 0047]) including:
a photodiode (PD, formed in silicon substrate; Figs 1,4; ¶ [0002, 0047]) in a semiconductor substrate;
a floating diffusion (FD) (the region corresponding to 16a or 16b of Fig 1, in the embodiment of Fig 10 {annotated in the included figure} ¶ [0007]) in the semiconductor substrate, wherein the FD accumulates charges generated in the photodiode (¶ [0016]);
a charge holding unit including a first wiring capacity (additional capacitance configured to include wiring capacitance of the Third Configuration Example; Figs 5,7,11; ¶ [0020-22,0060-63]) formed by a first wiring and a second wiring (comb-tooth wiring of M3 layer in Fig 11; ¶ [0063]), wherein the first wiring and the second wiring are in a first wiring layer (M3 layer; ¶ [0060-61]), and
a conversion efficiency switching switch (14a; Figs 5,7; ¶ [0050]), wherein the first wiring is electrically connected to a fixed potential (GND; in the same manner as shown for the lower connection of CsubFD in Figs 5,7, where, in the Third Configuration Example, the CsubFD represents the additional capacitance configured to include wiring capacitance), and
wherein the second wiring is electrically connected to the conversion efficiency switching switch (in the same manner that the upper connection of CsubFD in Figs 5,7 connects with switch 14a).
Regarding claim 2, Sano discloses the solid-state imaging element according to claim 1, wherein the charge holding unit is electrically connected to the FD (at least through GND, as shown in Figs 5,7 where CsubFD represents the charge holding unit, as explained under claim 1).
Regarding claim 3, Sano discloses the solid-state imaging element according to claim 1, wherein the first wiring is electrically connected to ground (GND) (as explained under claim 1).
Regarding claim 4, Sano discloses the solid-state imaging element according to claim 1, wherein the first wiring layer (M3; Fig 11) includes a portion in which a first portion of the first wiring runs in a first direction and a first portion of the second wiring runs in parallel with the first portion of the first wiring (the vertical portions of each of the first wiring and the second wiring {longitudinally linear portions}; ¶ [0063]).
Regarding claim 5, Sano discloses the solid-state imaging element according to claim 4, wherein in a plan view, the first portion overlaps at least a part of the photodiode. (This is explicitly disclosed for the first configuration example of Fig 4 described in ¶ [0049,0052]. Referencing Fig 11 for the third configuration example, it is clear that the vertical portions {first portions} of the M3 layer overlap the same light receiving area 21 {the photodiode} labeled in Fig 4).
Regarding claim 6, Sano discloses the solid-state imaging element according to claim 1, wherein at least a part of the second wiring is surrounded by the first wiring. (The comb-tooth pattern {Fig 11; ¶ [0063}) includes a surrounding configuration: each horizontal extension portion of the second wiring is surrounded on three sides by the adjacent horizontal extensions of the first wiring and the vertical portion connecting the adjacent horizontal extensions. A fourth side of the second wiring horizontal extension portion is surrounded by another vertical portion of the first wiring.)
Regarding claim 7, Sano discloses the solid-state imaging element according to claim 1, wherein in a plan view, the first wiring includes a U-shape and the at least a part of the second wiring is in the U-shape (The comb-tooth pattern {Fig 11; ¶ [0063}) includes a U-shape in a portion of each of the first wiring and the second wiring, the U-shape of the first wiring facing that of the second wiring, as shown in Fig 11.).
Regarding claim 8, Sano discloses the solid-state imaging element according to claim 1, wherein the first wiring includes an extending portion extending in a first direction (the vertical portions of the comb-tooth pattern of the first wiring {longitudinally linear portions}; Fig 11; ¶ [0063]) and a bending portion bending in a determined portion (the extending portions, extending in a horizontal direction and forming U-shaped patterns with the vertical portion; Fig 11).
Regarding claim 9, Sano discloses the solid-state imaging element according to claim 1, but does not disclose the pixel further including a third wiring and a fourth wiring, wherein the third wiring and the fourth wiring are in a second wiring layer that is a different layer from the first wiring layer, and wherein the charge holding unit further includes a second wiring capacity formed by the third wiring and the fourth wiring.
However, Sano discloses in the First Configuration Example of Fig 4 (¶ [0046-56]) a third wiring in the M2 layer and a fourth wiring in the M3 layer, where a second wiring capacity is formed between the two wiring layers. It would have been obvious to a person having ordinary skill in the art to combine the Fig 4 example having a wiring capacity in different layers with the Fig 11 example of the Third Configuration having a first wiring and a second wiring in a same M3 layer to arrive at claim 9. This represents a prima facie case of obviousness in a manner of combining prior art elements according to known methods to yield predictable results: (1) Sano discloses a wiring capacity formed in a same layer and also discloses another exemplary wiring capacity formed in different layers. One of ordinary skill in the art may have combined these two types of known wiring capacities according to claim 9 according to routine wire routing/layout methods known in the art. Thus combined, a third wiring and fourth wiring on a same layer different from the M3 layer of first wiring and the second wiring would have predictably performed in the same manner as did the first wiring and second wiring on the M3 layer of Third Example, as would the combination of the first wiring capacity on the M3 layer and second wiring capacity on a different layer. See MPEP 2143.I.A
Regarding claim 10, Sano discloses the solid-state imaging element according to claim 9, but does not disclose wherein the third wiring or the fourth wiring is electrically connected to the fixed potential; however, it would have been obvious in the combination explained under claim 9 to configure the second wiring capacity in the same manner as the first wiring capacity of claim 1, and to connect the third wiring or fourth wiring to the fixed potential in the same manner as for first wiring of claim 1 and in accordance with the circuit configuration of Figs 5 and 7, where one side of the capacitance (CsubFD; Figs 5,7) is connected to ground (fixed potential) and the other side is connected to the conversion efficiency switch.
Regarding claim 11, Sano discloses the solid-state imaging element according to claim 9, but does not disclose wherein the third wiring or the fourth wiring is electrically connected to ground (GND); however, it would have been obvious in the combination explained under claim 9 to configure the second wiring capacity in the same manner as the first wiring capacity of claim 1, and to connect the third wiring or fourth wiring to the GND fixed potential in the same manner as for first wiring of claim 1 and in accordance with the circuit configuration of Figs 5 and 7, where one side of the capacitance (CsubFD; Figs 5,7) is connected to ground and the other side is connected to the conversion efficiency switch.
Regarding claim 12, Sano discloses the solid-state imaging element according to claim 1, wherein the conversion efficiency switching switch (14a; Figs 5,7) is a conversion efficiency switching transistor (¶ [0050]).
Regarding claim 13, Sano discloses the solid-state imaging element according to claim 1, wherein the conversion efficiency switching transistor is a metal oxide semiconductor (MOS) transistor (This would have been obvious to person of ordinary skill in the art since this is an CMOS image sensor (Abst; ¶ [0046]), a MOS transistor is depicted for the switch 14a in the circuit diagram of Figs 5,7, and MOS transistors are commonly used in the art in pixel circuits).
Regarding claim 14, Sano discloses the solid-state imaging element according to claim 1, wherein one end of the conversion efficiency switching switch (14a; Figs 5,7) is connected to a drain of a transfer transistor and to the FD (CFD; as shown in Figs 5,7).
Regarding claim 15, Sano discloses the solid-state imaging element according to claim 14, wherein a cathode of the photodiode is connected to a source of the transfer transistor (as shown in Figs 5,7).
Regarding claim 16, Sano discloses the solid-state imaging element according to claim 1, wherein one end of the conversion efficiency switching switch (14a; Figs 5,7) and the FD (CFD; Figs 5,7) are connected to a gate of an amplification transistor (SF; as shown in Figs 5,7).
Regarding claim 17, Sano discloses the solid-state imaging element according to claim 1, wherein one end of the conversion efficiency switching switch (14a; Figs 5,7), the FD (CFD; Figs 5,7), and a gate of an amplification transistor (SF; Figs 5,7) are connected to a source of a reset transistor (RST; as shown in Figs 5,7).
Regarding claim 18, Sano discloses the solid-state imaging element according to claim 1, wherein a capacitance of the FD is increased when the conversion efficiency switching switch is turned on (additional capacitance is enabled; ¶ [0056]).
Regarding claim 19, Sano discloses the solid-state imaging element according to claim 1, wherein the increased capacitance includes a capacitance of the conversion efficiency switching switch itself, a diffusion capacitance, and the charge holding unit (wiring capacitance); (¶ [0020-22]).
Regarding claim 20, Sano discloses an electronic device (digital camera, for example; ¶ [0073]), comprising:
a solid-state imaging element (CMOS image sensor; ¶ [0046]), including:
a pixel, (one of eight shown in Fig 10 as described in paragraphs [0019, 0047]) including:
a photodiode (PD, formed in silicon substrate; Figs 1,4; ¶ [0002, 0047]) in a semiconductor substrate;
a floating diffusion (FD) (the region corresponding to 16a or 16b of Fig 1, in the embodiment of Fig 10 {annotated in the included figure} ¶ [0007]) in the semiconductor substrate, wherein the FD accumulates charges generated in the photodiode (¶ [0016]);
a charge holding unit including a first wiring capacity (additional capacitance configured to include wiring capacitance of the Third Configuration Example; Figs 5,7,11; ¶ [0020-22,0060-63]) formed by a first wiring and a second wiring (comb-tooth wiring of M3 layer in Fig 11; ¶ [0063]), wherein the first wiring and the second wiring are in a first wiring layer (M3 layer; ¶ [0060-61]), and
a conversion efficiency switching switch (14a; Figs 5,7; ¶ [0050]), wherein the first wiring is electrically connected to a fixed potential (GND; in the same manner as shown for the lower connection of CsubFD in Figs 5,7, where, in the Third Configuration Example, the CsubFD represents the additional capacitance configured to include wiring capacitance), and
wherein the second wiring is electrically connected to the conversion efficiency switching switch (in the same manner that the upper connection of CsubFD in Figs 5,7 connects with switch 14a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yamakawa; Shinya (US 2013/0001403; the prior art discloses an imaging element having a switch for connecting or disconnecting an additional capacitor with a floating diffusion);
Koga; Fumihiko; (WO 2016121521; the prior art discloses an imaging element having a switch for connecting or disconnecting an additional capacitance with a floating diffusion, and a MOS capacitor as the additional capacitance. Note: US 2017/0373107 is used as the English translation).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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