DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12 July 2024 complies with the provisions of 37 CFR 1.97. Accordingly, the examiner has considered the information disclosure statement; please see attached forms PTO-1449.
Drawings
The drawings submitted have been reviewed and determined to facilitate understanding of the invention. The drawings are accepted as submitted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9, 11, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication No. US 2019/0333905 to Raghunathan et al. (hereinafter “US1”), cited in Applicant’s IDS.
Regarding Claim 9, US1 describes a method (see Figs 1-2 and [0041]-[0054]) comprising:
forming a waveguide over a substrate (105; see [0047]);
forming a first photonic component (130) and a second photonic component (135) in the waveguide;
forming an interconnect structure (125/127) over the waveguide, wherein the interconnect structure is electrically connected to the first photonic component and the second photonic component; and
bonding a first die (122 ASIC1) and a second die (122 ASIC2) to the interconnect structure, wherein the first die is electrically coupled to the second die by a conductive line of the interconnect structure (see [0044]).
Regarding Claim 11, US1 describes the first die overlapping the first photonic component and the second die overlaps the second photonic component (see Figs 1a-1c).
Regarding Claim 12, US1 describes the first die electrically coupled to the first photonic component by the interconnect structure, wherein the second die is electrically coupled to the second photonic component by the interconnect structure (see Figs 1a-1c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6-8, 10, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US1.
Regarding Claim 1, US1 describes a method (see Figs 1-2 and [0041]-[0054]) comprising:
processing a first substrate (105) to form a waveguide (see [0047]);
forming a photonic device (130/135) on the first substrate, wherein the photonic device is optically coupled to the waveguide (see [0047], [0050]);
forming a first contact pad (at 127) over the first substrate, wherein the first contact pad is electrically connected to the photonic device (see Fig 1a);
forming a redistribution structure on a second substrate (110), wherein the redistribution structure comprises a second contact pad (at vias shown in Fig 1a); and
bonding a semiconductor die (122/123) to the first contact pad and to the second contact pad (see [0044], [0051].
US1 does not describe patterning a silicon layer on a first substrate to form a waveguide. US1 is silent as to the manner of formation and structure of the waveguides formed on the described photonic integrated circuits (“PICs”) (see [0047]). However, patterning a silicon layer is a well-known method of forming waveguides on PICs. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use such a well-known waveguide formation method in the method of US1. The motivation for doing so would have been to apply a known technique to a known method ready for improvement to yield predictable results.
Regarding Claims 2-3, US1 does not describe forming a grating coupler as claimed. However, grating couplers including a mirror thereover with a fiber attached to the reflector to provide optical coupling between the optical fiber and the grating are well-known in the art. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to form such a well-known grating coupler and reflector structure in the method of US1 in place of forming the V-groove coupling structure described by US1. The motivation for doing so would have been to make a simple substitution of one known element for another to obtain predictable results.
Regarding Claim 4, US1 describes patterning the silicon layer to form an edge coupler (via the V-groove structure, see [0053]).
Regarding Claim 6, US1 describes forming a second through via extending through the second substrate (see Fig 1a, [0040]), wherein the second through via is connected to the redistribution structure.
Regarding Claim 7, US1 describes attaching the first substrate and the second substrate to an interconnect substrate (via 115/128, see [0051]).
Regarding Claim 8, US1 describes the semiconductor die overlapping the first substrate and the second substrate (see Fig 1a).
Regarding Claim 10, US1 describes the method of Claim 1, as discussed above herein. US1 does not describe the forming of the waveguide comprising patterning a silicon layer. US1 is silent as to the manner of formation and structure of the waveguides formed on the described photonic integrated circuits (“PICs”) (see [0047]). However, patterning a silicon layer is a well-known method of forming waveguides on PICs. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use such a well-known waveguide formation method in the method of US1. The motivation for doing so would have been to apply a known technique to a known method ready for improvement to yield predictable results.
Regarding Claim 16, US1 describes a system comprising:
a first package (see Figs 1a-1c) comprising:
a first package substrate (attached to 115/128, see [0051]);
a first optical interposer (105) attached to the first package substrate, wherein the first optical interposer comprises a first waveguide optically (see [0047]) coupled to a first photonic device (130/135); and
a first semiconductor device (122/123) attached to the first optical interposer, wherein the first semiconductor device is electrically coupled to the first photonic device (via 125/127);
and
a first optical fiber extending from the first package, wherein the first optical fiber is optically coupled to the first waveguide (see [0027], [0047], [0050]).
US1 does not describe the system comprising a second package or the optical fiber extending to the second package and optically coupled to the second waveguide. US1 describes the use of the described package in electro-optical systems for high speed digital communications (see [0003]-[0004]). High speed digital communications inherently requires transmitting and receiving components. The structure of US1 describes transmitting portions (associated with 130) and receiving portions (associated with 135). Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the described package structure of US1 for first and second packages of a high speed digital communications system. The motivation for doing so would have been to allow for high speed digital communications (see [0003]-[0004]). Such a system would have a single optical fiber coupled to the waveguides of the first and second packages to allow for communication from a transmitting portion and a receiving portion (see [0047], [0050]).
Regarding Claim 17, US1 describes the first package comprising an edge coupler (V-groove structures), wherein the first optical fiber is optically coupled to the first waveguide by the edge coupler (see [0047], [0052]).
Regarding Claim 18, US1 does not describe the second package comprising a grating coupler, wherein the first optical fiber is optically coupled to the second waveguide by the grating coupler. Grating couplers optical coupled to an optical fiber are well-known in the art. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to form such a well-known grating coupler structure in place of the V-groove coupling structure described by US1. The motivation for doing so would have been to make a simple substitution of one known element for another to obtain predictable results.
Regarding Claim 20, US1 does not describe a third package comprising a third waveguide; and a second optical fiber extending from the first package to the third package, wherein the second optical fiber is optically coupled to the first waveguide and the third waveguide. As discussed with regards to Claim 16, it would have been obvious to connect multiple of the packages of US1 to enable high speed digital communications. Further, US1 describes the package structure comprising multiple receiving (135) and transmitting (130) portions (see Figs 1a-1c). Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to incorporate a third package having the structure described by US1 with an additional optical fiber connecting the waveguides of the first and third packages. The motivation for doing so would have been to allow for communications to more than two locations.
Allowable Subject Matter
Claims 5, 13-15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 describes forming a first through via extending through the first substrate, wherein the semiconductor die is connected to the first through via.
Claim 13 describes forming through vias extending through the substrate, wherein the through vias are electrically coupled to the interconnect structure.
Claims 14-15 describe forming a photonic switch network in the waveguide.
Claim 19 describes the first package comprising a heat spreader over the first package substrate and the first semiconductor device.
These limitations represent subject matter not described or reasonably suggested, in conjunction with the further limitations of the present claims, by the prior art of record.
Conclusion
The prior art cited in the attached form PTO-892 are made of record and considered pertinent to applicant's disclosure. The cited prior art described various methods and/or systems relating to optical packages with waveguides, photonic devices, redistribution structures, and semiconductor dies.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY RAHLL whose telephone number is (571)272-2356. The examiner can normally be reached M-F 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERRY RAHLL/Primary Examiner, Art Unit 2874
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