DETAILED ACTION
This action is responsive to application No. 18/771,200 filed on July 12, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
This action is responsive to the application filed on 07/12/2024. Accordingly, pending in this Office action are claims 1-8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2016/0013287) in view of Kamath (US 2002/0151188).
Regarding Claim 1, Yamamoto (see, e.g., Fig. 1), teaches a semiconductor device comprising:
a support substrate SB (see, e.g., par. 0031);5
an insulating layer BX formed on the support substrate SB (see, e.g., par. 0031);
a semiconductor layer SL formed on the insulating layer BX (see, e.g., par. 0031);
a first source region D1 (i.e., left source region D1) formed in the semiconductor layer SL (see, e.g., par. 0038);
a first drain region D1 (i.e., right drain region D1) formed in the semiconductor layer SL so as to be separated from the first source region D110 (see, e.g., par. 0038);
a first channel formation region sandwiched between the first source region D1 and the first drain region D1 (see, e.g., pars. 0039, 0069, 0072);
a first gate insulating film GF formed on the first channel formation region (see, e.g., par. 0033); and
a first gate electrode G1 formed on the first gate insulating 15film GF (see, e.g., par. 0033),
a second source region D2 (i.e., left source region D2) formed in the semiconductor layer SL so as to be separated from the first source region D1 and the first drain region D1 (see, e.g., par. 0046);
a second drain region D2 (i.e., right drain region D2) formed in the semiconductor layer SL so as to be separated from the first source region D110, the first drain region D1, and the second source region D2 (see, e.g., par. 0046);
a second channel formation region sandwiched between the second source region D2 and the second drain region D2 (see, e.g., pars. 0044, 0069, 0072);
a second gate insulating film GF formed on the second channel formation region so as to be separated from the first gate insulating film GF (see, e.g., par. 0045); and
a second gate electrode G2 formed on the second gate insulating 15film GF so as to be separated from the first gate electrode G1 (see, e.g., par. 0045),
wherein:
a thickness of the semiconductor layer SL is 2 nm or more and 24 nm or less (see, e.g., par. 0032).
Further, Yamamoto teaches a first field effect transistor Q1 including the first gate insulating film GF, the first gate electrode G1, the first channel formation region, the first source region D1, and the first drain region D1, and a second field effect transistor Q2 including the second gate insulating film GF, the second gate electrode G2, the second channel formation region, the second source region D2, and the second drain region D2 (see, e.g., pars. 0032-0033).
Yamamoto is silent with respect to the claim limitations that the first filed effect transistor Q1 is a component of a first analog circuit and the second field effect transistor Q2 is a component of a first digital circuit, wherein the first analog circuit includes at least one or more the first field effect transistors.
Kamath (see, e.g., Fig. 1), on the other hand, teaches that the first filed effect transistor 24 is a component of a first analog circuit and the second field effect transistor 22 is a component of a first digital circuit having different desired characteristics. The digital transistor is optimized for high-frequency switching and low-voltage/high-drive operation, while the analog transistor is optimized for linear response and higher supply voltage (see, e.g., par. 0005).
It would have been obvious to one of ordinary skill in the art at the time of filing to have in Yamamoto’s device, the first filed effect transistor being a component of a first analog circuit and the second field effect transistor being a component of a first digital circuit, wherein the first analog circuit includes at least one or more the first field effect transistors, as taught by Kamath, to realize a hybrid integrated circuit containing both a digital switching transistor optimized for high-frequency switching and low-voltage/high-drive operation, and an analog transistor optimized for linear response and higher supply voltage.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2016/0013287) in view of Fujita (US 5,336915).
Regarding Claim 4, Yamamoto (see, e.g., Fig. 1), teaches a semiconductor device comprising:
a support substrate SB (see, e.g., par. 0031);
an insulating layer BX formed on the support substrate SB (see, e.g., par. 0031);
a semiconductor layer SL formed on the insulating layer BX (see, e.g., par. 0031);
a first source region D1 (i.e., left source region D1) formed in the semiconductor layer SL (see, e.g., par. 0038);
a first drain region D1 (i.e., right drain region D1) formed in the semiconductor layer SL so as to be separated from the first source region D110 (see, e.g., par. 0038);
a first channel formation region sandwiched between the first source region D1 and the first drain region D1 (see, e.g., pars. 0039, 0069, 0072);
a first gate insulating film GF formed on the first channel formation region (see, e.g., par. 0033);
a first gate electrode G1 formed on the first gate insulating 15film GF (see, e.g., par. 0033);
a second source region D2 (i.e., left source region D2) formed in the semiconductor layer SL so as to be separated from the first source region D1 and the first drain region D1 (see, e.g., par. 0046);
a second drain region D2 (i.e., right drain region D2) formed in the semiconductor layer SL so as to be separated from the first source region D110, the first drain region D1, and the second source region D2 (see, e.g., par. 0046);
a second channel formation region sandwiched between the second source region D2 and the second drain region D2 (see, e.g., pars. 0044, 0069, 0072);
a second gate insulating film GF formed on the second channel formation region so as to be separated from the first gate insulating film GF (see, e.g., par. 0045); and
a second gate electrode G2 formed on the second gate insulating 15film GF so as to be separated from the first gate electrode G1 (see, e.g., par. 0045),
wherein:
a thickness of the semiconductor layer SL is 2 nm or more and 24 nm or less (see, e.g., par. 0032).
Further, Yamamoto teaches a first field effect transistor Q1 including the first gate insulating film GF, the first gate electrode G1, the first channel formation region, the first source region D1, and the first drain region D1, and a second field effect transistor Q2 including the second gate insulating film GF, the second gate electrode G2, the second channel formation region, the second source region D2, and the second drain region D2 (see, e.g., pars. 0032-0033).
Yamamoto is silent with respect to the claim limitations that the first filed effect transistor Q1 is a component of an analog circuit of an A/D converter and the second field effect transistor Q2 is a component of a digital circuit of the A/D converter.
Fujita (see, e.g., Fig. 1-3), on the other hand, teaches a semiconductor integrated circuit having both a digital circuit and an analog circuit formed on the same semiconductor substrate. In particular, Fujita discloses a first well region in which a digital circuit is formed and a separate second well region in which and analog circuit comprising CMOS transistors is formed. Further, it teaches an A/D converter associated with the analog and digital circuit portions. An A/D converter may be divided between the analog and digital portions of the integrated circuit, thereby providing the analog processing circuitry and digital processing circuitry required for analog-to-digital conversion (see, e.g., col. 4, ll. 14-59).
It would have been obvious to one of ordinary skill in the art at the time of filing, to modify the semiconductor device of Yamamoto to implement the first and second FETs in respective analog and digital circuit portions of an A/D converter as taught by Fujita. Such a modification would have been a predictable use of known CMOS semiconductor circuit technology to provide analog and digital functionality on the same semiconductor device, while obtaining the known benefits of integration, reduced interconnects, and reduced area.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2016/0013287) in view of Fujita (US 5,336915) and further in view of Kamath (US 2002/0151188).
Regarding Claim 5, Yamamoto and Fujita teach all aspects of claim 4. They are silent with respect to the claim limitation that a dielectric withstand voltage between the first source region and the first drain region in the first field effect transistor is higher than a dielectric withstand voltage between the second source region and the second drain region in the second field effect transistor.
Kamath (see, e.g., Fig. 1), on the other hand, teaches that a dielectric withstand voltage between the first source region 38 and the first drain region 40 in the first field effect transistor 24 is higher than a dielectric withstand voltage between the second source region 28 and the second drain region 30 in the second field effect transistor 22. The higher voltage is required to develop a sufficient magnitude for the analog signals and to provide the analog transistors with enough voltage range to allow them to operate in their linear transconductance or response range (see, e.g., pars. 0005-0006).
It would have been obvious to one of ordinary skill in the art at the time of filing, to modify the semiconductor device of Yamamoto and Fujita to implement a dielectric withstand voltage between the first source region and the first drain region in the first field effect transistor higher than a dielectric withstand voltage between the second source region and the second drain region in the second field effect transistor, as taught by Kamath, to develop a sufficient magnitude for the analog signals and to provide the analog transistors with enough voltage range to allow them to operate in their linear transconductance or response range.
Regarding Claim 6, Yamamoto and Fujita teach all aspects of claim 4. They are silent with respect to the claim limitation that a thickness of the first gate insulating film is larger than a thickness of the second gate insulating film.
Kamath (see, e.g., Fig. 1), on the other hand, teaches that a thickness of the first gate insulating film is larger than a thickness of the second gate insulating film. In analog linear transistors, the gate insulator is kept relatively thick, because a relatively thick gate insulator more effectively establishes linear response characteristics with better noise immunity, the higher operating voltages are also better tolerated by a thicker gate insulator, particularly for reliability considerations. In digital switching transistors, the gate insulator is kept as thin as possible, because the thinner insulator will result in higher frequency switching capability. Also, the lower operating voltages of digital switching transistors require a thinner insulator to maximize driving current (see, e.g., par. 0006).
It would have been obvious to one of ordinary skill in the art at the time of filing, to modify Yamamoto’s device to implement a thickness of the first gate insulating film being larger than a thickness of the second gate insulating film, as taught by Kamath, to more effectively establish linear response characteristics with better noise immunity and to better tolerate the higher operating voltages, particularly for reliability considerations.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2016/0013287) in view of Fujita (US 5,336915) and further in view of Chuang (US 2011/0221009).
Regarding Claim 7, Yamamoto and Fujita teach all aspects of claim 4. Yamamoto does not teach that a gate length of the first gate electrode is larger than a gate length of the second gate electrode.
Chuang (see, e.g., Fig. 2), on the other hand, teaches that a gate length 56 of the first gate electrode 51 is larger than a gate length 60 of the second gate electrode 48, because analog applications have stricter linearity requirements than digital applications for proper operation of the integrated circuit (see, e.g., par. 0023).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify Yamamoto’s/Fujita’s device and implement a gate length of the first gate electrode being larger than a gate length of the second gate electrode, to properly operate the integrated circuit due to the stricter linearity requirements needed for analog applications.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
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/Nelson Garces/Primary Examiner, Art Unit 2814
