Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-6 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 6, and 7 of copending Application No. 17/750450 (Aoki, US 20220384185 A1) in view of Ponnuswamy (US 20100300888 A1) and Yamashita (US 20150162181 A1).
Regarding independent claim 1, Aoki claims A method for processing a surface of a semiconductor wafer (Claim 2, A method of processing a surface of a SiC substrate, comprising…”) comprising steps of: causing a pulsed to flow through the semiconductor wafer as an anode in an electrolyte solution, thereby anodizing an object surface (Claim 1, “…a pulsed current having a period greater than 0.01 seconds and less than or equal to 20 seconds for anodizing the workpiece surface…”); and selectively removing an oxide generated on the object surface during the anodization (Claim 2, “…and selectively removing, with the grinding wheel layer, an oxide generated on the workpiece surface through anodization.”). However, Aoki does not claim a pulsed current of which the current density is larger than or equal to 20mA/cm2.
However, in the same field of endeavor, Ponnuswamy teaches a pulsed current of which the current density is larger than or equal to 20mA/cm2 ([0050], “A multiwave process that had an immersion current density of approximately 20 mA/cm2 and a pulse current density of approximately 40 mA/cm2…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the surface processing method of Aoki with the pulsed current density of Ponnuswany so as to lead “to a more uniform fill across an array” (Ponnuswamy, [0052]).
Regarding dependent claim 2, Aoki, as previously modified by Ponnuswamy, claims the method according to claim 1. However, as previously combined, they do not teach wherein a period of the pulsed current is from 0.5 sec to 5.0 sec and a duty ratio of the pulsed current is from 0.5 to 0.9.
However, Ponnuswamy further teaches wherein a period of the pulsed current is from 0.5 sec to 5.0 sec ([0065], “In other embodiments, the micropulse waveform has a period of about 100 to 2000 ms…”, (This is in the range given)) and a duty ratio of the pulsed current is from 0.5 to 0.9 ([0065], “The duty cycle (i.e., the pulse duration divided by the pulse period) of the micropulse waveform may be about 1% to 99%...”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the surface processing method as described by the combination of Aoki and Ponnuswamy with the period and duty ratio of the pulsed current of Ponnuswany so that “the duration of a micropulse may be about 0.5 ms to 495 ms” (Ponnuswamy, [0065]).
Regarding dependent claim 3, Aoki, as previously modified by Ponnuswamy, claims the method according to claim 1, and further claims wherein in a state where a surface processing pad having a grinding stone layer is disposed such that the grinding stone layer faces the object surface, an oxide is selectively removed by the grinding stone layer (Claim 2, “…and disposing a grinding wheel layer of a surface processing pad to face the workpiece surface and selectively removing, with the grinding wheel layer, an oxide generated on the workpiece surface through anodization.”).
Regarding dependent claim 4, Aoki, as previously modified by Ponnuswamy, claims the method according to claim 3, and further claims wherein polishing is used for selectively removing an oxide by the grinding stone layer (Claim 6, “…the selective removal of the oxide generated on the workpiece surface with the grinding wheel layer.”, Claim 7, “The method according to claim 6, wherein the grinding wheel layer grinds or polishes the workpiece surface anodized by application of the pulsed current.”).
Regarding dependent claim 5, Aoki, as previously modified by Ponnuswamy, claims the method according to claim 1. However, as previously combined, they do not teach wherein the oxide is selectively removed by a solution in which the oxide is soluble.
However, in the same field of endeavor, Yamashita teaches wherein the oxide is selectively removed by a solution in which the oxide is soluble ([0121], “…after the oxide film remaining on the surface of the semiconductor wafer W is completely removed by immersing the semiconductor wafer W in a hydrofluoric acid solution.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the surface processing method as described by the combination of Aoki and Ponnuswamy with the solution of Yamashita so that the “flatness…of the surface of the semiconductor wafer can be further improved” (Yamashita, [0121]).
Regarding dependent claim 6, Aoki, as previously modified by Ponnuswamy, teaches the method according to claim 1, and further teaches, wherein the semiconductor wafer is a SiC wafer (Claim 1, “A surface processing apparatus for a SiC substrate…”).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ponnuswamy (US 20100300888 A1), in view of Yamamoto (US 20020037684 A1).
Regarding independent claim 1, Ponnuswamy teaches a method for processing a surface of a semiconductor wafer ([0002], “More specifically, this invention relates to an electroplating method for depositing electrically conductive materials on a semiconductor wafer for integrated circuit manufacturing.”) comprising steps of: causing a pulsed current of which the current density is larger than or equal to 20mA/cm2 to flow through the semiconductor wafer ([0050], “A multiwave process that had an immersion current density of approximately 20 mA/cm2 and a pulse current density of approximately 40 mA/cm2…”) as an anode in an electrolyte solution, thereby anodizing an object surface ([0082], “In certain configurations of the plating cell, a distinct electrolyte is circulated through the portion of the plating cell in which the anode is contained and mixing with the main plating solution is prevented using sparingly permeable membranes or ion selective membranes.”). However, Ponnuswamy does not teach and selectively removing an oxide generated on the object surface during the anodization.
However, in the same field of endeavor, Yamamoto teaches selectively removing an oxide generated on the object surface during the anodization ([0004], “For example, in case an oxide film is polished, a grinding stone is used…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the surface processing method of Ponnuswamy with the selective oxide removal of Yamamoto so that “the surface of the semiconductor wafer can be polished” (Yamamoto, [0003]).
Regarding dependent claim 2, Ponnuswamy, as previously modified by Yamamoto, teaches the method according to claim 1, and further teaches wherein a period of the pulsed current is from 0.5 sec to 5.0 sec ([0065], “In other embodiments, the micropulse waveform has a period of about 100 to 2000 ms…”, (This is in the range given)) and a duty ratio of the pulsed current is from 0.5 to 0.9 ([0065], “The duty cycle (i.e., the pulse duration divided by the pulse period) of the micropulse waveform may be about 1% to 99%...”).
Regarding dependent claim 3, Ponnuswamy, as previously modified by Yamamoto, teaches the method according to claim 1. However, as previously combined, they do not teach wherein in a state where a surface processing pad having a grinding stone layer is disposed such that the grinding stone layer faces the object surface, an oxide is selectively removed by the grinding stone layer.
However, Yamamoto further teaches wherein in a state where a surface processing pad having a grinding stone layer is disposed such that the grinding stone layer faces the object surface, an oxide is selectively removed by the grinding stone layer ([0004], “In this method, however, instead of abrasive grains or powder, a grinding stone comprising abrasive grains buried in a polishing material on the surface of the rotary tool is used. For example, in case an oxide film is polished, a grinding stone is used…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the surface processing method as described by the combination of Ponnuswamy and Yamamoto with the grinding stone of Yamamoto so that “the surface of the semiconductor wafer can be polished” (Yamamoto, [0003]).
Regarding dependent claim 4, Ponnuswamy, as previously modified by Yamamoto, teaches the method according to claim 3. Yamamoto further teaches wherein polishing is used for selectively removing an oxide by the grinding stone layer ([0004], “In this method, however, instead of abrasive grains or powder, a grinding stone comprising abrasive grains buried in a polishing material on the surface of the rotary tool is used. For example, in case an oxide film is polished, a grinding stone is used…”).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ponnuswamy (US 20100300888 A1), in view of Yamamoto (US 20020037684 A1), and Yamashita (US 20150162181 A1).
Regarding dependent claim 5, Ponnuswamy, as previously modifed by Yamamoto, teaches the method according to claim1. However, as previously combined, they do not teach wherein the oxide is selectively removed by a solution in which the oxide is soluble.
However, in the same field of endeavor, Yamashita teaches wherein the oxide is selectively removed by a solution in which the oxide is soluble ([0121], “…after the oxide film remaining on the surface of the semiconductor wafer W is completely removed by immersing the semiconductor wafer W in a hydrofluoric acid solution.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the surface processing method as described by the combination of Ponnuswamy and Yamamoto with the solution of Yamashita so that the “flatness…of the surface of the semiconductor wafer can be further improved” (Yamashita, [0121]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ponnuswamy (US 20100300888 A1), in view of Yamamoto (US 20020037684 A1), and Takenouchi (US 20180369990 A1).
Regarding dependent claim 6, Ponnuswamy, as previously modified by Yamamoto, teaches the method according to claim 1. However, as previously combined, they do not teach wherein the semiconductor wafer is a SiC wafer.
However, in the same field of endeavor, Takenouchi teaches wherein the semiconductor wafer is a SiC wafer ([0037], “The workpiece W, which is of a circular contour as depicted in FIG. 1, is a semiconductor wafer made of a hard-to-grind material of SiC, for example.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the surface processing method as described by the combination of Ponnuswamy and Yamamoto with the SiC wafer of Takeouchi so that “a number of devices” can be made on the face of the wafer (Takeouchi, [0037]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20040053499 A1, pertaining to a method of polishing a substrate.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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