CTNF 18/771,306 CTNF 77082 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Abstract The abstract of the disclosure is objected to because: In line 1, the term “ may ” is not understood because the term “ may ” recites a broad range or limitation by linking terms and a narrow range or limitation within the broad range or limitation is considered indefinite since the resulting claim does not clearly set forth the metes and bounds of the Patent protection desired. Please, change “ may include ” to - - includes - - for proper reading. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-2, 6-9, 11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (U.S. Patent 9,313,891) in view of Lee (U.S. Patent 9,332,841) . As to claim 1, Jung discloses a printed circuit board (PCB-100) as shown in figures 1-6 comprising: a main body (100) having an edge and a first surface on which a semiconductor chip (150 or 160) is provided; a first pin (122) comprising: a first tab (the body of the pin 122) extending in a first direction parallel to the first surface toward the edge (110E) of the main body and configured to receive a first signal corresponding to communication between the outside and the semiconductor chip (150); and a first tie-bar (124) protruding from an end of the first tab (122) toward the edge of the main body (110), the first tie-bar (124) having a first length along the first direction; and a second pin (122) adjacent to the first pin, the second pin comprising: a second tab (the body of the pin 122) extending in the first direction toward the edge (110E) of the main body and configured to receive an applied a ground voltage of a ground; and a second tie-bar (124) protruding from an end of the second tab toward the edge of the main body. Jung does not specifically disclose the second tie-bar having a second length that is greater than the first length along the first direction. Lee teaches a connection structure of circuit board (100) as shown in figures 1-6 comprising the second tie-bar (the pad 120 of the wire 130) having a second length that is greater than the first length (of the wire 130 having a pad 110) along the first direction. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Lee employed in the PCB of Jung in order to provide excellent electrical connection structure to external device. Regarding claim 2, Jung as modified by Lee teaches in figure 1 that a first sub-interval between the edge of the main body (100) and an end of the first tie-bar is greater than a second sub-interval between the edge of the main body and an end of the second tie-bar (the distance from the pad 110 to the edge is greater than the distance from the pad 120 to the edge). Regarding claim 6, Jung as modified by Lee discloses the main body (110) further comprises: a notch (not label but shown the recess in figure 1, hereafter called N) at the edge (110E) of the main body; a first edge region (the right side of the pin/tab 122) on a first side of the main body; and a second edge region (the left side of the pin/tab 122) on a second side of the main body, wherein the notch (N) is between the first and second edge regions, wherein the first and second pins (122) are both in the first edge region or the second edge region, and wherein the first and second tie-bars (124) are located on a same side of the first pin and the second pin, respectively. Regarding claim 7, Jung as modified by Lee discloses the main body (110) further comprises: a notch (N) at the edge (110E) of the main body; a first edge region (the right side) on a first side of the main body; and a second edge region (the left side) on a second side of the main body, wherein the notch (N) is between the first and second edge regions, wherein the first pin (122) is in the first edge region, wherein the first tie-bar (124) is located on a first side of the first pin, wherein the second pin (122) is in the second edge region, and wherein the second tie-bar (124) is located on a second side of the second pin, the second side of the second pin being different from the first side of the first pin. Regarding claim 8, Jung as modified by Lee discloses further comprising a third pin (122 on the bottom side) comprising: a third tab (bottom of the pin 122) extending in the first direction toward the edge of the main body and configured to receive a second signal that is different from the first signal; and a third tie-bar (the bottom 124) protruding from an end of the third tab toward the edge of the main body, the third tie-bar having a third length that is less than the second length along the first direction. Regarding claim 9, Jung as modified by Lee discloses the first to third pins (122) are sequentially arranged in a second direction perpendicular to the first direction, wherein the first and second pins (122) are adjacent to each other, and wherein the second and third pins (122) are adjacent to each other. As to claim 20, Jung discloses a method of manufacturing a printed circuit board (PCB-100), the method comprising: forming an internal wiring layer (130-1a) on a plate layer (110); providing an insulating layer (140-1) on the plate layer and the internal wiring layer; forming a contact hole (H1) penetrating the insulating layer; forming an external wiring layer (150-1) on the insulating layer (140), see figures 12A-12F; forming a first pin (122), the first pin comprising: a first tab (the body of the pin 122) to which a signal (copper foil) is applied and a first tie-bar (124) having a first length; forming a second pin (122), to form a resultant product, the second pin comprising: a second tab (the body of the pin 122) to which a ground voltage is applied and a second tie-bar having a second length, and separating the resultant product along a cutting line into the PCB (100) having a first edge portion on which the first pin and the second pin are provided. Jung does not specifically disclose the second tie-bar having a second length that is greater than the first length along the first direction. Lee teaches a connection structure of circuit board (100) as shown in figures 1-6 comprising the second tie-bar (the pad 120 of the wire 130) having a second length that is greater than the first length (of the wire 130 having a pad 110) along the first direction. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Lee employed in the PCB of Jung in order to provide excellent electrical connection structure to external device . 07-21-aia AIA Claim (s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goodwin (U.S. Patent 8,951,070) in view of Kanapathippillai et al. (U.S. 2008/0094808) . As to claim 11, Goodwin discloses a memory module as shown in figure 2 comprising: a semiconductor chip (not shown but the SATA having NAND flash memory chips); and a printed circuit board (PCB-10) comprising: a main body (the body of PCB-10) on which the semiconductor chip (150) is provided; a first pin (101b) spaced apart from an edge of the main body by a first distance, the first pin (101b) comprising an end terminal to which a first signal (column 4, line 30) is applied; and a second pin (101b) spaced apart from the edge of the main body (10) by a second distance that is less than the first distance, the second pin (101a) comprising an end terminal to which a second supply voltage is applied (column 4, line 29). Goodwin does not specifically disclose the second supply voltage having a level lower than a level of a first supply voltage corresponding to a power supply to the semiconductor chip. Kanapathippillai a memory module (100A) as shown in figures 1A-1B comprising the second supply voltage having a level lower than a level of a first supply voltage corresponding to a power supply to the semiconductor chip (115 or 133), para-0025+. It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Kanapathippillai employed in the PCB of Goodwin in order to provide minimize power consumption . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-5, 1-, and 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached 8am-5pm, M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2847 Application/Control Number: 18/771,306 Page 2 Art Unit: 2847 Application/Control Number: 18/771,306 Page 3 Art Unit: 2847 Application/Control Number: 18/771,306 Page 4 Art Unit: 2847 Application/Control Number: 18/771,306 Page 5 Art Unit: 2847 Application/Control Number: 18/771,306 Page 6 Art Unit: 2847 Application/Control Number: 18/771,306 Page 7 Art Unit: 2847 Application/Control Number: 18/771,306 Page 8 Art Unit: 2847 Application/Control Number: 18/771,306 Page 9 Art Unit: 2847
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