DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
The present application, 18/771448, claims priority to Provisional Application 63/534512, filed on August 24, 2023. The claim for priority is acknowledged as properly supported under 35 U.S.C. § 119(e) for the provisional application.
Claim Objections
Claims 7 and 17 objected to because of the following informalities:
Claim 7 and 17: “wherein apply the first time adjustment and the second time adjustment” Improper subject-verb agreement. Will be read as ‘Applying’
Appropriate correction is required.
Specification
The disclosure is objected to because of the following informalities:
¶[0088]: “The term ‘coupling’ (e.g., "electrically coupling") may refer to condition of moving from an open-circuit relationship between components.” Word omitted. Will be read as ‘may refer to the condition…’
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-16, and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2019/0215199 A1 to Timothy M. Hollis, et al. (hereafter Hollis).
Regarding Independent Claim 1, Hollis discloses an apparatus, comprising:
at least one memory device (A memory device: Hollis, ¶[0013]); and
at least one controller coupled with the at least one memory device (A memory controller connected the memory device: Hollis, ¶[0014]) and configured to cause the apparatus to:
identify data for transmitting over a conductive path as a multilevel signal (Transmitting a multi-level signal: Hollis, ¶[0015]), the data comprising
first data processed by a first signaling component for transmitting over the conductive path (A first data processed by a first signaling component: Hollis, ¶[0033]) and
second data processed by a second signaling component for transmitting over the conductive path (A second data processed by a second signaling component: Hollis, ¶[0033]);
apply a first time adjustment to a clock signal received at the first signaling component (Adjusting the timing of the clock signal of first data output: Hollis, ¶[0036]);
apply a second time adjustment to the clock signal received at the second signaling component (Adjusting the timing of the clock signal of second data output: Hollis, ¶[0036]); and
generate the multilevel signal based at least in part on
the first signaling component generating a first portion of the multilevel signal comprising the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component generating a second portion of the multilevel signal comprising the second data (A second driver configured to output second data: Hollis, ¶[0034]),
wherein applying the first time adjustment and the second time adjustment to the clock signal (Applying a timing offset to the first and/or second data: Hollis, ¶[0037]) is associated with aligning
a timing of the first portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the first data transmitted: Hollis, ¶[0037]) and
a timing of the second portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the second data transmitted: Hollis, ¶[0037]).
Regarding Claim 2 and the substantially similar limitations of Claim 14, Hollis discloses the apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to:
transmit the multilevel signal via a pad contacting the conductive path (A signaling interface configured to generate or decode multi-level signals: Hollis, ¶[0032])
based at least in part on generating the multilevel signal (Based on the the multi-level signal: Hollis, ¶[0032]),
the pad coupled with the first signaling component and the second signaling component (The driver connected with each of the signaling legs: Hollis, ¶[0032]).
Regarding Claim 3, Hollis discloses the apparatus of claim 1, wherein
the first signaling component comprises a first serialization component operable to serialize the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component comprises a second serialization component operable to serialize the second data (A second driver configured to output second data: Hollis, ¶[0034]).
Regarding Claim 4, Hollis discloses the apparatus of claim 3, wherein the at least one controller is further configured to cause the apparatus to:
serialize the first data
based at least in part on the first time adjustment to the clock signal (Adjusting the first data signal based on the timing adjustment: Hollis, ¶[0037]),
wherein generating the first portion of the multilevel signal is based at least in part on serializing the first data (Generating the first data: Hollis, ¶[0034]; Serializing the first data: Hollis, ¶[0070])); and
serialize the second data
based at least in part on the second time adjustment to the clock signal (Adjusting the second data signal based on the timing adjustment: Hollis, ¶[0037]),
wherein generating the second portion of the multilevel signal is based at least in part on serializing the second data (Generating the second data: Hollis, ¶[0034]; Serializing the second data: Hollis, ¶[0070]).
Regarding Claim 5, Hollis discloses the apparatus of claim 1, wherein applying the first time adjustment to the clock signal is configured to cause the apparatus to:
receive the clock signal at a first adjustable delay circuit (Receive the clock signal at first delay component 405-b: Hollis, ¶[0073]); and
apply a first delay to the clock signal (Apply the first delay to the clock signal: Hollis, ¶[0073])
via the first adjustable delay circuit (Via delay component 405-b: Hollis, ¶[0073]),
the first delay corresponding to the first time adjustment (The first delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]).
Regarding Claim 6, Hollis discloses the apparatus of claim 1, wherein applying the second time adjustment to the clock signal is configured to cause the apparatus to:
receive the clock signal at a second adjustable delay circuit (Receive the clock signal at second delay component 405-c: Hollis, ¶[0073]); and
apply a second delay to the clock signal (Apply the second delay to the clock signal: Hollis¶[0073]),
via the second adjustable delay circuit (Via delay component 405-c: Hollis, ¶[0073]),
the second delay corresponding to the second time adjustment (The second delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]).
Regarding Claim 9 and the substantially similar limitations of Claim 19, Hollis discloses the apparatus of claim 1, wherein:
the first signaling component comprises
a first driver operable to transmit the first portion of the multilevel signal (A first driver capable of transmitting the first portion of the signal: Hollis, ¶[0034]), and
the second signaling component comprises
a second driver operable to transmit the second portion of the multilevel signal (A second driver capable of transmitting the second portion of the signal: Hollis, ¶[0034]).
Regarding Claim 10, Hollis discloses the apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to:
transmit the first portion of the multilevel signal based at least in part on the first time adjustment to the clock signal (Transmitting the first portion of the signal based at least in part on the first delay: Hollis, ¶[0037]); and
transmit the second portion of the multilevel signal based at least in part on the second time adjustment to the clock signal (Transmitting the second portion of the signal based at least in part on the second delay: Hollis, ¶[0037]).
Regarding Claim 11, Hollis discloses the apparatus of claim 1, wherein aligning the timing of the first portion of the multilevel signal and the timing of the second portion of the multilevel signal is configured to cause the apparatus to:
increase a read window margin between a first read window of the first portion of the multilevel signal and a second read window of the second portion of the multilevel signal (Proper synchronization of data signals increasing the width of the eye diagram: Hollis, ¶[0042]).
Regarding Claim 12, Hollis discloses the apparatus of claim 1, wherein
the multilevel signal is modulated using a modulation scheme that comprises three levels (Indicating three or more levels in the modulation scheme: Hollis, ¶[0019]).
Regarding Independent Claim 13, Hollis discloses a non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
identify data for transmitting over a conductive path as a multilevel signal (Transmitting a multi-level signal: Hollis, ¶[0015]), the data comprising
first data processed by a first signaling component for transmitting over the conductive path (A first data processed by a first signaling component: Hollis, ¶[0033]) and
second data processed by a second signaling component for transmitting over the conductive path (A second data processed by a second signaling component: Hollis, ¶[0033]);
apply a first time adjustment to a clock signal received at the first signaling component (Adjusting the timing of the clock signal of first data output: Hollis, ¶[0036]);
apply a second time adjustment to the clock signal received at the second signaling component (Adjusting the timing of the clock signal of second data output: Hollis, ¶[0036]); and
generate the multilevel signal based at least in part on
the first signaling component generating a first portion of the multilevel signal comprising the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component generating a second portion of the multilevel signal comprising the second data (A second driver configured to output second data: Hollis, ¶[0034]),
wherein applying the first time adjustment and the second time adjustment to the clock signal (Applying a timing offset to the first and/or second data: Hollis, ¶[0037]) is associated with aligning
a timing of the first portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the first data transmitted: Hollis, ¶[0037]) and
a timing of the second portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the second data transmitted: Hollis, ¶[0037]).
Regarding Claim 15, Hollis discloses the non-transitory computer-readable medium of claim 13, wherein
the first signaling component comprises
a first serialization component operable to serialize the first data (A first driver configured to output first data: Hollis, ¶[0034])
based at least in part on the first time adjustment to the clock signal (Adjusting the first data signal based on the timing adjustment: Hollis, ¶[0037]) and
the second signaling component comprises
a second serialization component operable to serialize the second data (A second driver configured to output second data: Hollis, ¶[0034])
based at least in part on the second time adjustment to the clock signal (Adjusting the second data signal based on the timing adjustment: Hollis, ¶[0037]).
Regarding Claim 16, Hollis discloses the non-transitory computer-readable medium of claim 13, wherein
the instructions to apply the first time adjustment to the clock signal are executable by the processor to:
receive the clock signal at a first adjustable delay circuit (Receive the clock signal at first delay component 405-b: Hollis, ¶[0073]); and
apply a first delay to the clock signal (Apply the first delay to the clock signal: Hollis, ¶[0073]),
via the first adjustable delay circuit (Via delay component 405-b: Hollis, ¶[0073]),
the first delay corresponding to the first time adjustment (The first delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]); and
wherein the instructions to apply the second time adjustment to the clock signal are executable by the processor to:
receive the clock signal at a second adjustable delay circuit (Receive the clock signal at second delay component 405-c: Hollis, ¶[0073]); and
apply a second delay to the clock signal (Apply the second delay to the clock signal: Hollis¶[0073]),
via the second adjustable delay circuit (Via delay component 405-c: Hollis, ¶[0073]),
the second delay corresponding to the second time adjustment (The second delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]).
Regarding Independent Claim 20, Hollis discloses a method, comprising:
identifying data for transmitting over a conductive path as a multilevel signal (Transmitting a multi-level signal: Hollis, ¶[0015]), the data comprising
first data processed by a first signaling component for transmitting over the conductive path (A first data processed by a first signaling component: Hollis, ¶[0033]) and
second data processed by a second signaling component for transmitting over the conductive path (A second data processed by a second signaling component: Hollis, ¶[0033]);
apply a first time adjustment to a clock signal received at the first signaling component (Adjusting the timing of the clock signal of first data output: Hollis, ¶[0036]);
apply a second time adjustment to the clock signal received at the second signaling component (Adjusting the timing of the clock signal of second data output: Hollis, ¶[0036]); and
generate the multilevel signal based at least in part on
the first signaling component generating a first portion of the multilevel signal comprising the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component generating a second portion of the multilevel signal comprising the second data (A second driver configured to output second data: Hollis, ¶[0034]),
wherein applying the first time adjustment and the second time adjustment to the clock signal (Applying a timing offset to the first and/or second data: Hollis, ¶[0037]) is associated with aligning
a timing of the first portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the first data transmitted: Hollis, ¶[0037]) and
a timing of the second portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the second data transmitted: Hollis, ¶[0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-8 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0215199 A1 to Timothy M. Hollis, et al. (hereafter Hollis) in view of US 11,726,721 B2 to Byongmo moon, et al. (hereafter Moon).
Regarding Claim 7 and the substantially similar limitations of Claim 17, Hollis discloses the apparatus of claim 1, but fails to disclose storing the delay parameters in a register. Moon, however, discloses an apparatus as in Claim 1 wherein the at least one controller is further configured to cause the apparatus to:
store an indication of the first time adjustment and the second time adjustment (Storing a determined weight, delay, in a register or fuse: Moon, col.6:49-50)
in a programmable read-only memory (Storing the weight in a programmable read only mode register: Moon, col.8:51-53); and
wherein apply the first time adjustment and the second time adjustment to the clock signal is based at least in part on accessing the programmable read-only memory (Adjusting the signal timing based on the data stored in the register: Moon, col.6:54-56).
Moon discloses the process of performing an initial test to determine appropriate signal weight and storing this delay data in a register eliminates the need to perform additional retrainings (Moon, col.6:25-35), which would require greater resource use (Moon, col.1:51-52). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the long-term delay parameter storage of Moon with the individual delay paths of Hollis, with a reasonable expectation of success. Both inventions are well known in the field of managing signal delay in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 8 and the substantially similar limitations of Claim 18, Hollis discloses the apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to:
measure a misalignment (Determining a misalignment: Hollis, ¶[0035]) between
the timing of the first portion of the multilevel signal transmitted over the conductive path (The misalignment being between the first data signal: Hollis, ¶[0035]) and
the timing of the second portion of the multilevel signal transmitted over the conductive path (And the second data signal: Hollis, ¶[0035]);
determine the first time adjustment and the second time adjustment based at least in part on measuring the misalignment (Adjusting the data signals based on the delay based on the misalignment: Hollis, ¶[0037]); and
applying the first time adjustment (Applying the first delay: Hollis, ¶[0037) and
applying the second time adjustment (Applying the second delay: Hollis, ¶[0037).
Hollis does not disclose storing the first and second time adjustment parameters in a programmable read-only memory. While it Hollis does disclose applying the first and second time adjustment, it does not disclose doing so based at least in part on the data stored in programmable read-only memory. Moon, however, discloses an apparatus as in Claim 8, configured to:
store the first time adjustment and the second time adjustment (Storing a determined weight, delay, in a register or fuse: Moon, col.6:49-50)
in a programmable read-only memory (Storing the weight in a programmable read only mode register: Moon, col.8:51-53), and
applying the first time adjustment and applying the second time adjustment are based at least in part on the storing (Adjusting the signal timing based on the data stored in the register: Moon, col.6:54-56).
Moon discloses the process of performing an initial test to determine appropriate signal weight and storing this delay data in a register eliminates the need to perform additional retrainings (Moon, col.6:25-35), which would require greater resource use (Moon, col.1:51-52). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the long-term delay parameter storage of Moon with the individual delay paths of Hollis, with a reasonable expectation of success. Both inventions are well known in the field of managing signal delay in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,281,935 B2 to Han Soo Lee, et al.: Disclosing serializing data and generating time adjusted multi-level signals.
US 11,594,267 B2 to Mingyu Lee, et al.: Disclosing a memory device with a multilevel signal with timed signal modulation.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/PHO M LUU/Primary Examiner, Art Unit 2824 02/27/2026.