DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
An Information Disclosure Statement has not been entered. Applicant is reminded of the duty to disclose material information under 37 CFR 1.56. If applicant wishes to have an Information Disclosure Statement made of record, please submit form PTO/SB/08, along with any statements and fees required by 37 CFR 1.97, prior to or along with the payment of the issue fee.
Response to Amendment
The amendment filed June 2, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 1, 4-8, 10, 13, and 14-20 have been amended. No claims have been added. No new matter has been added.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed March 3, 2026.
Claim Rejections - 35 USC § 112
Claim 16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are:
Claim 16 states: …”receive a clock signal at a first adjustable delay circuit; and apply, via the first adjustable delay circuit, a first delay to the clock signal, the first delay corresponding to the first time adjusted clock signal…” The intent of this language is inconsistent with claim 13 from which depends. Claim 13 states, in relevant part, “receive a first time adjusted clock signal from a first adjustable delay circuit at the first signaling component.” Therefore, taken together, the first adjustable delay circuit takes in a first delay, equivalent to the first time adjusted clock signal, delays the original clock signal by the first time adjusted clock signal, and then outputs the same first time adjusted clock signal. This conclusion is illogical and makes the intent of the limitation indefinite. A similar problem affects the second time adjusted clock signal limitation of the claim.
For the purposes of compact prosecution, the phrase ‘corresponding to the first time adjusted clock signal’ will be interpreted to mean the ‘first time adjustment.’ A similar interpretation will be applied to the second time adjusted clock signal. This is not a clear interpretation of this limitation, however, and the claim will be considered incomplete unless further amended.
Claims 8 and 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted elements are:
Claim 8 and the substantially similar Claim 18, as amended, disclose the controller being configured to, “…store the first time adjustment and the second time adjustment in a programmable read-only memory, wherein receiving the first time adjusted clock signal and receiving the second time adjusted clock signal are based at least in part on the storing.” It is unclear how the controller is intended to receive a previously adjusted clock signal based in part or in whole on the storage of a time adjustment that has already been applied.
For the purposes of compact prosecution, this limitation will be read as a repeating the delay previously applied to the clock signal, permitting the controller to either actively apply the delay signal internally or passively receiving the previously adjusted clock signal. This is not a clear interpretation of the limitation, however, and the claim will be considered incomplete unless further amended.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-6, 9-16, and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2019/0215199 A1 to Timothy M. Hollis, et al. (hereafter Hollis).
Regarding Amended Independent Claim 1, Hollis discloses an apparatus, comprising:
at least one memory device (A memory device: Hollis, ¶[0013]); and
at least one controller coupled with the at least one memory device (A memory controller connected the memory device: Hollis, ¶[0014]) and configured to cause the apparatus to:
identify data for transmitting over a conductive path as a multilevel signal (Transmitting a multi-level signal: Hollis, ¶[0015]), the data comprising
first data processed by a first signaling component for transmitting over the conductive path (A first data processed by a first signaling component: Hollis, ¶[0033]) and
second data processed by a second signaling component for transmitting over the conductive path (A second data processed by a second signaling component: Hollis, ¶[0033]);
receive a first time adjusted clock signal from a first adjustable delay circuit (Receiving a first time adjusted clock signal 445-a at multiplexer 410-a: Hollis, Figure 4b) at the first signaling component (Adjusting the timing of the clock signal of first data output: Hollis, ¶[0036]);
receive a second time adjusted clock signal from a second adjustable delay circuit (Receiving a second time adjusted clock signal 450-a at multiplexer 415-a: Hollis, Figure 4b) at the second signaling component (Adjusting the timing of the clock signal of second data output: Hollis, ¶[0036]); and
generate the multilevel signal based at least in part on
the first signaling component generating a first portion of the multilevel signal comprising the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component generating a second portion of the multilevel signal comprising the second data (A second driver configured to output second data: Hollis, ¶[0034]),
wherein receiving the first time adjusted clock signal and the second time adjusted clock signal (Applying a timing offset to the first and/or second data: Hollis, ¶[0037]; Alternatively, receiving the time adjustment from an external source: Hollis, ¶[0037]) is associated with aligning
a timing of the first portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the first data transmitted: Hollis, ¶[0037]) and
a timing of the second portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the second data transmitted: Hollis, ¶[0037]).
Regarding Claim 2 and the substantially similar limitations of Claim 14, Hollis discloses the apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to:
transmit the multilevel signal via a pad contacting the conductive path (A signaling interface configured to generate or decode multi-level signals: Hollis, ¶[0032])
based at least in part on generating the multilevel signal (Based on the the multi-level signal: Hollis, ¶[0032]),
the pad coupled with the first signaling component and the second signaling component (The driver connected with each of the signaling legs: Hollis, ¶[0032]).
Regarding Claim 3, Hollis discloses the apparatus of claim 1, wherein
the first signaling component comprises a first serialization component operable to serialize the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component comprises a second serialization component operable to serialize the second data (A second driver configured to output second data: Hollis, ¶[0034]).
Regarding Amended Claim 4, Hollis discloses the apparatus of claim 3, wherein the at least one controller is further configured to cause the apparatus to:
serialize the first data
based at least in part on the first time adjusted clock signal (Adjusting the first data signal based on the timing adjustment: Hollis, ¶[0037]),
wherein generating the first portion of the multilevel signal is based at least in part on serializing the first data (Generating the first data: Hollis, ¶[0034]; Serializing the first data: Hollis, ¶[0070])); and
serialize the second data
based at least in part on the second time adjusted clock signal (Adjusting the second data signal based on the timing adjustment: Hollis, ¶[0037]),
wherein generating the second portion of the multilevel signal is based at least in part on serializing the second data (Generating the second data: Hollis, ¶[0034]; Serializing the second data: Hollis, ¶[0070]).
Regarding Amended Claim 5, Hollis discloses the apparatus of claim 1, wherein the at least one controller is configured to cause the apparatus to:
receive a clock signal at a first adjustable delay circuit (Receive the clock signal at first delay component 405-b: Hollis, ¶[0073]); and
apply a first delay to the clock signal (Apply the first delay to the clock signal: Hollis, ¶[0073])
via the first adjustable delay circuit (Via delay component 405-b: Hollis, ¶[0073]),
the first delay corresponding to the first time adjusted clock signal (The first delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]).
Regarding Amended Claim 6, Hollis discloses the apparatus of claim 1, wherein the at least one controller is configured to cause the apparatus to:
receive a clock signal at a second adjustable delay circuit (Receive the clock signal at second delay component 405-c: Hollis, ¶[0073]); and
apply a second delay to the clock signal (Apply the second delay to the clock signal: Hollis¶[0073]),
via the second adjustable delay circuit (Via delay component 405-c: Hollis, ¶[0073]),
the second delay corresponding to the second time adjusted clock signal (The second delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]).
Regarding Claim 9 and the substantially similar limitations of Claim 19, Hollis discloses the apparatus of claim 1, wherein:
the first signaling component comprises
a first driver operable to transmit the first portion of the multilevel signal (A first driver capable of transmitting the first portion of the signal: Hollis, ¶[0034]), and
the second signaling component comprises
a second driver operable to transmit the second portion of the multilevel signal (A second driver capable of transmitting the second portion of the signal: Hollis, ¶[0034]).
Regarding Amended Claim 10, Hollis discloses the apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to:
transmit the first portion of the multilevel signal based at least in part on the first time adjusted clock signal (Transmitting the first portion of the signal based at least in part on the first delay: Hollis, ¶[0037]); and
transmit the second portion of the multilevel signal based at least in part on the second time adjusted clock signal (Transmitting the second portion of the signal based at least in part on the second delay: Hollis, ¶[0037]).
Regarding Claim 11, Hollis discloses the apparatus of claim 1, wherein aligning the timing of the first portion of the multilevel signal and the timing of the second portion of the multilevel signal is configured to cause the apparatus to:
increase a read window margin between a first read window of the first portion of the multilevel signal and a second read window of the second portion of the multilevel signal (Proper synchronization of data signals increasing the width of the eye diagram: Hollis, ¶[0042]).
Regarding Claim 12, Hollis discloses the apparatus of claim 1, wherein
the multilevel signal is modulated using a modulation scheme that comprises three levels (Indicating three or more levels in the modulation scheme: Hollis, ¶[0019]).
Regarding Amended Independent Claim 13, Hollis discloses a non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
identify data for transmitting over a conductive path as a multilevel signal (Transmitting a multi-level signal: Hollis, ¶[0015]), the data comprising
first data processed by a first signaling component for transmitting over the conductive path (A first data processed by a first signaling component: Hollis, ¶[0033]) and
second data processed by a second signaling component for transmitting over the conductive path (A second data processed by a second signaling component: Hollis, ¶[0033]);
receive a first time adjusted clock signal from a first adjustable delay circuit (Receiving a first time adjusted clock signal 445-a at multiplexer 410-a: Hollis, Figure 4b) at the first signaling component (Adjusting the timing of the clock signal of first data output: Hollis, ¶[0036]);
receive a second time adjusted clock signal from a second adjustable delay circuit (Receiving a second time adjusted clock signal 450-a at multiplexer 415-a: Hollis, Figure 4b) at the second signaling component (Adjusting the timing of the clock signal of second data output: Hollis, ¶[0036]); and
generate the multilevel signal based at least in part on
the first signaling component generating a first portion of the multilevel signal comprising the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component generating a second portion of the multilevel signal comprising the second data (A second driver configured to output second data: Hollis, ¶[0034]),
wherein receiving the first time adjusted clock signal and the second time adjusted clock signal (Applying a timing offset to the first and/or second data: Hollis, ¶[0037] ; Alternatively, receiving the time adjustment from an external source: Hollis, ¶[0037]) is associated with aligning
a timing of the first portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the first data transmitted: Hollis, ¶[0037]) and
a timing of the second portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the second data transmitted: Hollis, ¶[0037]).
Regarding Amended Claim 15, Hollis discloses the non-transitory computer-readable medium of claim 13, wherein
the first signaling component comprises
a first serialization component operable to serialize the first data (A first driver configured to output first data: Hollis, ¶[0034])
based at least in part on the first time adjusted clock signal (Adjusting the first data signal based on the timing adjustment: Hollis, ¶[0037]) and
the second signaling component comprises
a second serialization component operable to serialize the second data (A second driver configured to output second data: Hollis, ¶[0034])
based at least in part on the second time adjusted clock signal (Adjusting the second data signal based on the timing adjustment: Hollis, ¶[0037]).
Regarding Amended Claim 16, Hollis discloses the non-transitory computer-readable medium of claim 13, wherein
the instructions to receive the first time adjusted clock signal are executable by the processor to:
receive a clock signal at a first adjustable delay circuit (Receive the clock signal at first delay component 405-b: Hollis, ¶[0073]); and
apply a first delay to the clock signal (Apply the first delay to the clock signal: Hollis, ¶[0073]),
via the first adjustable delay circuit (Via delay component 405-b: Hollis, ¶[0073]),
the first delay corresponding to the first time adjusted clock signal (The first delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]); and
wherein the instructions to receive the second time adjusted clock signal are executable by the processor to:
receive the clock signal at a second adjustable delay circuit (Receive the clock signal at second delay component 405-c: Hollis, ¶[0073]); and
apply a second delay to the clock signal (Apply the second delay to the clock signal: Hollis¶[0073]),
via the second adjustable delay circuit (Via delay component 405-c: Hollis, ¶[0073]),
the second delay corresponding to the second time adjusted clock signal (The second delay corresponding to the appropriate time adjustment: Hollis, ¶[0073]).
Regarding Independent Claim 20, Hollis discloses a method, comprising:
identifying data for transmitting over a conductive path as a multilevel signal (Transmitting a multi-level signal: Hollis, ¶[0015]), the data comprising
first data processed by a first signaling component for transmitting over the conductive path (A first data processed by a first signaling component: Hollis, ¶[0033]) and
second data processed by a second signaling component for transmitting over the conductive path (A second data processed by a second signaling component: Hollis, ¶[0033]);
receiving a first time adjusted clock signal from a first adjustable delay circuit (Receiving a first time adjusted clock signal 445-a at multiplexer 410-a: Hollis, Figure 4b) at the first signaling component (Adjusting the timing of the clock signal of first data output: Hollis, ¶[0036]);
receiving a second time adjusted clock signal from a second adjustable delay circuit (Receiving a second time adjusted clock signal 450-a at multiplexer 415-a: Hollis, Figure 4b) at the second signaling component (Adjusting the timing of the clock signal of second data output: Hollis, ¶[0036]); and
generate the multilevel signal based at least in part on
the first signaling component generating a first portion of the multilevel signal comprising the first data (A first driver configured to output first data: Hollis, ¶[0034]) and
the second signaling component generating a second portion of the multilevel signal comprising the second data (A second driver configured to output second data: Hollis, ¶[0034]),
wherein receiving the first time adjusted clock signal and the second time adjusted clock signal (Applying a timing offset to the first and/or second data: Hollis, ¶[0037] ; Alternatively, receiving the time adjustment from an external source: Hollis, ¶[0037]) is associated with aligning
a timing of the first portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the first data transmitted: Hollis, ¶[0037]) and
a timing of the second portion of the multilevel signal transmitted over the conductive path (Adjusting the timing of the second data transmitted: Hollis, ¶[0037]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-8, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0215199 A1 to Timothy M. Hollis, et al. (hereafter Hollis) in view of US 11,726,721 B2 to Byongmo Moon, et al. (hereafter Moon).
Regarding Amended Claim 7 and the substantially similar limitations of Claim 17, Hollis discloses the apparatus of claim 1, but fails to disclose storing the delay parameters in a register. Moon, however, discloses an apparatus as in Claim 1 wherein the at least one controller is further configured to cause the apparatus to:
store an indication of a first time adjustment and a second time adjustment relative to a clock signal (Storing a determined weight, delay, in a register or fuse: Moon, col.6:49-50)
in a programmable read-only memory (Storing the weight in a programmable read only mode register: Moon, col.8:51-53),
based at least in part on the first time adjusted clock signal and the second time adjusted clock signal (Stored weights based at least in part on adjustments to the clock signal: Moon, Figure 4); and
wherein receiving the first time adjusted clock signal and the second time adjusted clock signal clock signal is based at least in part on accessing the programmable read-only memory (Adjusting the signal timing based on the data stored in the register: Moon, col.6:54-56).
Moon discloses the process of performing an initial test to determine appropriate signal weight and storing this delay data in a register eliminates the need to perform additional retrainings (Moon, col.6:25-35), which would require greater resource use (Moon, col.1:51-52). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the long-term delay parameter storage of Moon with the individual delay paths of Hollis, with a reasonable expectation of success. Both inventions are well known in the field of managing signal delay in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 8 and the substantially similar limitations of Claim 18, Hollis discloses the apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to:
measure a misalignment (Determining a misalignment: Hollis, ¶[0035]) between
the timing of the first portion of the multilevel signal transmitted over the conductive path (The misalignment being between the first data signal: Hollis, ¶[0035]) and
the timing of the second portion of the multilevel signal transmitted over the conductive path (And the second data signal: Hollis, ¶[0035]);
determine a first time adjustment and a second time adjustment to a clock signal based at least in part on measuring the misalignment (Adjusting the data signals based on the delay based on the misalignment: Hollis, ¶[0037]); and
wherein
receiving the first time adjusted clock signal (Applying the first delay: Hollis, ¶[0037) and
receiving the second time adjusted clock signal (Applying the second delay: Hollis, ¶[0037).
Hollis does not disclose storing the first and second time adjustment in a programmable read-only memory. While Hollis does disclose receiving the first and second time adjusted clock signal, it does not disclose doing so based at least in part on the data stored in programmable read-only memory. Moon, however, discloses an apparatus as in Claim 8, configured to:
store the first time adjustment and the second time adjustment (Storing a determined weight, delay, in a register or fuse: Moon, col.6:49-50)
in a programmable read-only memory (Storing the weight in a programmable read only mode register: Moon, col.8:51-53),
Receiving the first and second time adjusted clocks signals are based at least in part on the storing (Adjusting the signal timing based on the data stored in the register: Moon, col.6:54-56)
Moon discloses the process of performing an initial test to determine appropriate signal weight and storing this delay data in a register eliminates the need to perform additional retrainings (Moon, col.6:25-35), which would require greater resource use (Moon, col.1:51-52). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the long-term delay parameter storage of Moon with the individual delay paths of Hollis, with a reasonable expectation of success. Both inventions are well known in the field of managing signal delay in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed June 2, 2062 have been fully considered but they are not persuasive.
Applicant first highlights the amendments to independent Claim 1 and the similar changes made to the other independent claims, and then states Hollis fails to disclose the controller receiving a time adjusted clock signal (Applicant’s Arguments/Remarks, p.12¶2). This interpretation fails to take the full text of Hollis into account. Specifically, Hollis discloses either adjusting the timing of the signal in the path, as in Figure 4a, or adjusting the clock signal prior to propagating the transmission, as in Figure 4b, in which case the controller would be receiving the previously adjusted first and second time adjusted clock signals.
Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,281,935 B2 to Han Soo Lee, et al.: Disclosing serializing data and generating time adjusted multi-level signals.
US 11,594,267 B2 to Mingyu Lee, et al.: Disclosing a memory device with a multilevel signal with timed signal modulation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/PHO M LUU/ Primary Examiner, Art Unit 2824
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