DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 12 July 2024. In view of this communication, claims 1-14 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-11, and 13-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al. (US 20140167254 A1), hereinafter referred to as Yu et al.
Regarding claim 1, Yu et al. teaches a semiconductor device comprising:
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a semiconductor element (10) (Fig. 1, paragraph 11: the first substrate 10 is a semiconductor integrated circuit fabrication which includes transistors, resistors, diodes, etc.) including an element obverse surface and an element reverse surface facing away from each other in a thickness direction, and a first electrode terminal (28A) and a second electrode terminal (28D) disposed on the element obverse surface (Fig. 1, paragraph 10: bump structures 28A, 28D are disposed on the lower side of substrate 10);
a conductive member (204) electrically connected to the semiconductor element (10) (Fig. 1, paragraph 28: pads 204);
a first metal layer (208B) formed on the conductive member (204) and bonded to the first electrode terminal (28D) (Fig. 1, paragraph 29: connector 208B bonded to the first bump structure 28D via a solder joint 304); and
a second metal layer (208A) formed on the conductive member (204) and bonded to the second electrode terminal (28A) (Fig. 1, paragraph 29: connector 208A bonded to the second bump structure 28A via a solder joint 302),
wherein the first electrode terminal (28D) includes a first bonding surface facing the first metal layer (208B) (see Fig. 1 and paragraph 29),
the second electrode terminal (28A) includes a second bonding surface facing the second metal layer (208A) (see Fig. 1 and paragraph 29),
a first area (W2) of the first bonding surface (28D) is smaller than a second area (W1) of the second bonding surface (28A) (paragraph 16: the width W1 of the first pad 28A is less than the width W2 of the second pad 28D), and
a difference between a representative length (W4) of the first metal layer (208B) and a corresponding representative length (W2) of the first bonding surface (28D) is smaller than a difference between a representative length (W3) of the second metal layer (208A) and a corresponding representative length (W1) of the second bonding surface (28A) (paragraphs 16 and 28: the widths of the connectors 208A, 208B are substantially the same, resulting in a length W4 of connector 208B being closer to a length W2 than W1 because W2 is greater than W1).
Regarding claim 2, Yu et al. teaches the semiconductor device according to claim 1, wherein a ratio between a third area (W4) of the first metal layer (208B) and a fourth area (W3) of the second metal layer (208A) is within 10% of a ratio between the first area (W2) and the second area (W1) (paragraph 16: W2/W1 is between 0.84 and 1, while the widths W3 and W4 are equal, resulting in a difference of 0-16%).
Regarding claim 3, Yu et al. teaches the semiconductor device according to claim 2, wherein the ratio between the third area (W4) and the fourth area (W3) is equal to the ratio between the first area (W2) and the second area (W1) (paragraph 33 teaches that W4 may be greater than W3 which, when combined with the lengths disclosed in paragraph 16, may result in the claimed relationships between the areas).
Regarding claim 4, Yu et al. teaches the semiconductor device according to claim 2, wherein the second area (W1) is at least two times and at most four times greater than the first area (W2) (paragraph 16: the width W1 of pad 28A may be between 1µm and 10µm greater than W2, resulting in an area between two and four times greater than the area of pad 28D because W2 is between 15 and 30 µm).
Regarding claim 5, Yu et al. teaches the semiconductor device according to claim 1, wherein the first bonding surface (28D) and the first metal layer (208B) are circular, and the second bonding surface (28A) and the second metal layer (208A) are elliptical (paragraph 10: the pads and bumps may be circular or in the shape of an oval).
Regarding claim 6, Yu et al. teaches the semiconductor device according to claim 1, wherein the first bonding surface (28D) and the first metal layer (208B) are circular, the second bonding surface (28A) and the second metal layer (208A) are circular (paragraph 10: the pads may be circular).
Regarding claim 8, Yu et al. teaches the semiconductor device according to claim 1, wherein the first electrode terminal (28D) and the second electrode terminal (28A) contain Cu (paragraph 15: the metal pillars of 28A and 28D may be copper or an alloy thereof).
Regarding claim 9, Yu et al. teaches the semiconductor device according to claim 1, further comprising: a first bonding portion (304) interposed between the first bonding surface (28D) and the first metal layer (208) (Fig. 1, paragraph 29: connector 208B bonded to the first bump structure 28D via a solder joint 304); and a second bonding portion (302) interposed between the second bonding surface (28A) and the second metal layer (28D) (Fig. 1, paragraph 29: connector 208A bonded to the second bump structure 28A via a solder joint 302).
Regarding claim 10, Yu et al. teaches the semiconductor device according to claim 9, wherein the first bonding portion (304) and the second bonding portion (302) contain solder (paragraph 29).
Regarding claim 11, Yu et al. teaches the semiconductor device according to claim 1, wherein the semiconductor element (100) includes a plurality of third electrode terminals (28D) that are identical in shape to the first electrode terminal (28D), and a plurality of fourth electrode terminals (28A) that are identical in shape to the second electrode terminal (28A), and the first electrode terminal (28D) and the plurality of third electrode terminals (28D) are disposed on the element obverse surface at a location on a first side in a first direction orthogonal to the thickness direction, and the second electrode terminal (28A) and the plurality of fourth electrode terminals (28A) are disposed on the element obverse surface at a location on a second side in the first direction (see Fig. 1 and paragraph 10: bump structures 28A and 28D are arranged in arrays in regions 110 and 120, respectively).
Regarding claim 13, Yu et al. teaches the semiconductor device according to claim 1, wherein the conductive member (204) includes a first lead (204) and a second lead (204), the first metal layer (208B) is formed on the second lead (204), and the second metal layer (208A) is formed on the first lead (204) (paragraph 28: the pads 204 comprise a plurality of pads 204, upon which the connectors 208A and 208B are formed).
Regarding claim 14, Yu et al. teaches the semiconductor device according to claim 1, further comprising an insulating substrate (200A), wherein the conductive member (204) is a wiring formed on the insulating substrate (200A) (paragraph 28: contact pads 204 connect to vias 210 and other circuitry on the wiring board 200A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Orlowski et al. (US 20210007224 A1), hereinafter referred to as Orlowski et al.
Regarding claim 7, Yu et al. teaches the semiconductor device according to claim 1, but does not teach that the first metal layer and the second metal layer include: a first layer in contact with the conductive member and contains Ni; a second layer in contact with the first layer and contains Pd; and a third layer in contact with the second layer and contains Au.
Orlowski et al. does teach that the first metal layer and the second metal layer include: a first layer in contact with the conductive member and contains Ni; a second layer in contact with the first layer and contains Pd; and a third layer in contact with the second layer and contains Au (Orlowski et al. paragraph 40 teaches that a surface coating 36-2 made comprising nickel, palladium, and gold may be formed on the surfaces of contact pads 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first and second metal layers (208A, 208B) of Yu et al. from nickel, palladium, and gold as taught by Orlowski et al. because Orlowski et al. teaches that the Ni-Pd-Au coating improves the solderability of and reliability of the mounting pads. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious engineering choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Lin et al. (US 20140061897 A1), hereinafter referred to as Lin et al.
Regarding claim 12, Yu et al. teaches the semiconductor device according to claim 1, but does not teach that the conductive member includes a first lead, and the first metal layer and the second metal layer are formed on the first lead.
Lin et al. does teach that the conductive member includes a first lead, and the first metal layer and the second metal layer are formed on the first lead (Lin et al. Fig. 3B and paragraph 38 teach a single pad 16 with two pad portions 16P formed in order to provide connections to two metal pillars 28A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the pads (204) of Yu et al. as one pad with two points of connection as taught by Lin et al. because it has been held to be within the general skill of a worker in the art to make plural parts unitary as a matter of obvious engineering choice. In re Larson, 144 USPQ 347 (CCPA 1965); In re Lockart, 90 USPQ 214 (CCPA 1951).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US 11600590 B2)
Farooq et al. (US 20210175174 A1)
Ishikawa et al. (US 20200111731 A1)
Koduri (US 20190109110 A1)
Li (US 7564130 B1)
Chen et al. (US 7019407 B2)
Ference et al. (US 6858941 B2)
Giraudet (US 20040108363 A1)
Miyaki et al. (US 20030124770 A1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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