DETAILED ACTION
Claims 1–20 are pending. Claims 1, 8, and 15 are independent and examined on their merits below.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Benefit
This application does not claim the benefit of any prior-filed U.S. application under 35 U.S.C. 119(e), 120, 121, 365(c), or 386(c).
Foreign Priority
No foreign priority under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 365(a) or (b) has been claimed in this application. The Application Data Sheet of record does not identify any foreign application from which priority is claimed.
Information Disclosure
The information disclosure statement filed July 12, 2024 has been considered.
Specification
The specification is objected to for the following informalities. Applicant is required to make appropriate correction. No new matter.
Paragraph [0036]: “physical vapor diffusion (PVD)” is incorrect. The art term is physical vapor deposition (PVD).
Paragraph [0044] is blank. Delete the empty heading or supply the omitted paragraph.
Trademarks
The specification uses the following marks. Under MPEP § 608.01(v), a trademark must be shown as a proper adjective (capitalized; registered-mark symbol where the mark is registered) and not as the name of the goods themselves.
Paragraph [0046]: Cadence®, EVE®, and Mentor Graphics® already carry the registered-mark symbol. Acceptable. Confirm current ownership. No rejection is made.
Paragraph [0045]: “Blu-Ray,” “Rambus DRAM (RDRAM),” “Universal Serial Bus (USB),” “DDR,” “SDRAM,” “GDS II.” Blu-ray is a registered mark of the Blu-ray Disc Association; Rambus® / RDRAM® are Rambus marks; USB is a trademark of the USB Implementers Forum. Amend at least “Blu-Ray” to “Blu-ray® disc” (or delete the mark and recite “optical disc”). The remaining acronyms may remain if used generically after a first proper identification.
No other trade names were identified in paragraphs [0001]–[0047].
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4–7, 11–15, and 18–20 are rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
Claims 4, 11, and 18. “A sum of thicknesses of dielectric layers between adjacent metal layers disconnected from one another between the first metal layer and the second metal layer is less than a threshold.” No numerical threshold, no process-minimum, and no relationship to a breakdown voltage is recited. Paragraphs [0022]–[0024] describe which distances drop out of the sum when a via is present, but never name “a threshold.” The metes and bounds of “less than a threshold” cannot be determined. Amend to recite the sum of the disconnected dielectric thicknesses or to tie the threshold to a disclosed process minimum or breakdown criterion.
Claims 5 and 6 (and 12/13, 19/20). Claim 5 requires a third metal layer that “is a floating metal layer.” Claim 6 requires a third metal layer that “is connected to the first voltage reference level.” Both depend from claim 2 and use the same “third metal layer” phrase for mutually exclusive conditions. That is acceptable as alternative claims, but claim 6 as written can be read to require the same third metal layer already introduced in an optional sense. Prefer “a further metal layer” in one of the two claims.
Claim 12. The claim recites “further comprising a third metal layer” in a method claim without a forming step, unlike claim 13 (“further comprising forming a third metal layer”). Inconsistent method grammar. Amend claim 12 to “forming.”
Claims 7 and 14. Claim 7 recites “a floating metal layer is adjacent to each of the third metal layer and the fourth metal layer.” Claim 14 recites “a floating net is adjacent to each of the third metal layer and the fourth metal layer.” Paragraph [0017] defines “floating net” as a signal net with no connection to a voltage reference. The two claims are intended to cover FIG. 4 but use inconsistent terminology. Align the claims with one defined term.
Claim 14. Claim 14 depends from claim 13, which already recites “forming a third metal layer.” Claim 14 then recites “further comprising forming a third metal layer and fourth metal layer.” Double recitation of “a third metal layer” lacks antecedent clarity. Amend claim 14 to introduce only the fourth metal layer, or to depend from claim 9 and introduce both.
Claim 15. “A memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks” is awkward and it is unclear whether the tasks are executed by the integrated circuit that contains the capacitor or by some other processor. The capacitor limitations that follow do not use the memory. The claim is examined as a computing system that includes both the memory and the integrated circuit of claim 1. Applicant should tighten the nexus if that is the intended invention.
Claim Interpretation
The Office applies the broadest reasonable interpretation consistent with the specification (MPEP § 2111). For this Action:
“First metal layer connected to a first voltage reference level” and “second metal layer connected to a second voltage reference level” are the biased electrode plates of the capacitor (not signal nets 102/104 as mere routing). Signal nets 102/104 may be those plates or may be connected to those plates by vias, as in Schmidt ’450 FIG. 3.
“Floating metal layer” means a metal layer with no connection to a voltage reference level used by the integrated circuit (paragraph [0016]). A via that shorts two such layers to each other does not take them out of the “floating” class so long as the shorted node is not tied to Vref1 or Vref2.
“Via between a first pair of metal layers of the plurality” means a conductive interconnect that electrically shorts two of the floating intermediate plates to each other. Terminal vias that land only on a biased plate (or that strap odd plates to Vref1 and even plates to Vref2) do not meet this limitation.
Claim Rejections - 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless — (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
A. Claims 1, 8, and 15 as anticipated by Schmidt ’450 (US 11,881,450 B2)
Schmidt ’450 issued December 26, 2023, and is prior art under § 102(a)(1).
Schmidt ’450 FIG. 3 and claim 2 teach a multi-plate capacitor between two signal nets. The claimed first metal layer and second metal layer are the capacitor electrode plates that are electrically connected to those signal nets (and thus to the two voltage reference levels). They are not the signal-net routing lines themselves. Intermediate plates 130 sit between those two electrodes and float. Mapping:
Claim 1
Schmidt ’450
An integrated circuit comprising
On-die BEOL capacitor in an integrated circuit (FIG. 3)
a first metal layer connected to a first voltage reference level
First capacitor electrode plate. That plate is electrically connected (via 140) to a first signal net, and that signal net is at a first voltage reference level. The claimed first metal layer is the electrode, not the signal net.
a second metal layer connected to a second voltage reference level
Opposite capacitor electrode plate. That plate is electrically connected to a second signal net at a second voltage reference level. The claimed second metal layer is the electrode, not the signal net.
a plurality of metal layers with adjacent dielectric layers between the first and second metal layers
Plural intermediate plates 130 stacked between the two biased plates, each separated by dielectric
each of the plurality is a floating metal layer
Plates 130 are not connected to a voltage reference used by the IC (floating intermediates)
each is used to form a MIM capacitor of a plurality of MIMs between the first and second metal layers
Each adjacent pair of plates with intervening dielectric is a MIM; the stack is a plurality of series MIMs between the two Vrefs
Claim 8 is the method counterpart (forming the same stack) and is anticipated by the process that produces FIG. 3 of Schmidt ’450. Claim 15 adds a computing system with a memory storing instructions and an integrated circuit that executes those instructions and includes the capacitor of claim 1. Placing the FIG. 3 capacitor of Schmidt ’450 in a processor / memory system is the ordinary environment of an on-die decoupling or signal capacitor and is disclosed as an integrated-circuit use. Claim 15 is anticipated.
Schmidt ’450 does not anticipate claims 2, 3, 9, 10, 16, or 17. The vias 140 of Schmidt ’450 contact the biased electrode plates and the signal nets. They do not short a pair of the floating intermediate plates 130 to each other while those plates remain off both voltage references.
B. Claims 1, 8, and 15 as anticipated by Hsiao (US 2023/0387192 A1)
Hsiao published November 30, 2023 (filed May 25, 2022), and is prior art under § 102(a)(1).
Hsiao discloses a BEOL multi-plate MIM. In the cross-section relied upon: plate 25 is a bottom electrode, plate 50 is a top electrode, and plates 40 and 80 are intermediate conductive layers between 25 and 50, separated by dielectrics 35 / 45 / 85 / 55. Vias 75a / 75b contact the outer plates. Plates 40 and 80 are described as floating conductive layers.
Claim 1
Hsiao US 2023/0387192 A1
first metal layer at first Vref
Bottom plate 25 (biased; contacted by via 75a)
second metal layer at second Vref
Top plate 50 (biased; contacted by via 75b)
plurality of metal layers between them, each floating
Intermediate plates 40 and 80; each is a floating conductive layer (a plurality)
each forms a MIM of a plurality of MIMs between the two Vrefs
25/dielectric/40, 40/dielectric/80, and 80/dielectric/50 are series MIMs between the two biased plates
Claim 8 is anticipated by the method of forming that stack. Claim 15 is anticipated for the same computing-system reason given for Schmidt ’450.
Hsiao does not anticipate claims 2, 3, 9, 10, 16, or 17. Vias 75a and 75b land on the outer (biased) plates. No via shorts floating plate 40 to floating plate 80.
Claims not anticipated
Claims 2, 3, 9, 10, 16, and 17 add a first via between a first pair of the floating metal layers, and (claims 3, 10, 17) a second via between a second pair of those layers. Neither Schmidt ’450 nor Hsiao shows that via.
The Office has considered the additional art of record discussed with Applicant. Those references show terminal vias onto biased or tapped plates, odd/even plate strapping for parallel MIM, or discrete ceramic / isolator series capacitors. None anticipates a via whose only function is to short two intermediate plates that remain floating as to both voltage references. No § 102 rejection of claims 2–7, 9–14, or 16–20 is made.
No § 103 rejection is entered in this Action. The Office reserves the right to reconsider § 103 in a subsequent action if Applicant amends around the § 102 art in a way that reopens the via.
Allowable Subject Matter
Claims 2, 3, 9, 10, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Those claims require a via between a pair of the floating intermediate metal layers (and, in claims 3, 10, and 17, a second via between a second pair). The closest U.S. art that shows a via in a multi-plate MIM does not show that via.
U.S. Patent No. 11,881,450 B2 (Schmidt). Vias 140 connect capacitor electrode plates to the signal nets. They do not short two floating intermediate plates 130 to each other.
U.S. Patent Application Publication No. 2023/0387192 A1 (Hsiao). Vias 75a and 75b land on outer plates 25 and 50. Intermediate plates 40 and 80 remain separate. No via joins 40 to 80.
U.S. Patent Application Publication No. 2013/0270675 A1 (Childs). Vias 135 and 138 contact selected plates of a tri-plate stack, including a center tap. The via assigns a plate to a terminal or to a tap. It does not short two plates that both remain floating as to both voltage references.
U.S. Patent Application Publication No. 2007/0152295 A1 (Yeh). Contacts 113, 115, 117, and 119 wire complete two-plate MIMs in parallel. Those contacts are terminal wiring, not a via between two floating intermediates in one stack.
On this record, none of those references anticipates claims 2, 3, 9, 10, 16, or 17.
Claims 3–6, 10–14, and 17–20 depend from the via claims. They contain allowable subject matter because they depend from claims 2, 9, or 16.
Claim 7 depends from claim 1 and does not require the via of claim 2. Claim 7 recites a third metal layer and a fourth metal layer in the same metal track, disconnected from one another and connected to different voltage levels, with a floating metal layer adjacent to each of those layers using the same dielectric layer. That is the same-track arrangement of FIG. 4.
Schmidt ’450 and Hsiao are vertical multi-plate stacks between two continuous signal nets. They do not show two disconnected metals in one track, at different voltages, sharing one adjacent floating plate and one dielectric. Childs and Yeh likewise wire plates as terminals or as parallel MIMs; they do not teach that same-track split. Claim 7 is therefore allowable over the art applied against claim 1. There is no counterpart of claim 7 depending from claim 8 or claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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18 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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