DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/12/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,166,037. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 17, Pat '037 discloses, in claims 1 and 2, a method, comprising:
epitaxially growing a first nanostructured layer on a substrate; depositing a dielectric layer on the first nanostructured layer; epitaxially growing a second nanostructured layer on the dielectric layer; forming a polysilicon structure on the first nanostructured layer, the dielectric layer, and the second nanostructured layer; forming a first source/drain region in the first nanostructured layer; forming a second source/drain region in the second nanostructured layer; and replacing the polysilicon structure and the second nanostructured layers with a gate structure ("forming a superlattice structure with first and second nanostructured layers and a nanostructured dielectric layer on a substrate; forming a polysilicon structure around the first and second nanostructured layers and the nanostructured dielectric layer of the superlattice structure; forming a first conductivity type S/D region within a first portion of the S/D opening; forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening; replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers" and “the forming the superlattice structure comprises: epitaxially growing a first stack of semiconductor layers on the substrate; depositing a dielectric layer on the first stack of semiconductor layers; depositing a seed layer on the dielectric layer; and epitaxially growing a second stack of semiconductor layers”, in claims 1 and 2 of Pat '037, is interpreted as the same limitation).
Claims 1-4, 8-9 and 18-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 of U.S. Patent No. 12,166,037 in view of Lin (US 2022/0216340).
Regarding claim 1, Pat '037 discloses, in claim 16, a semiconductor device, comprising:
a substrate; a first nanostructured channel region disposed on the substrate;
a second nanostructured channel region; a layer disposed between and in contact with the first nanostructured channel region and the second nanostructured channel region; and a gate structure surrounding the first and second nanostructured channel regions ("a substrate; first and second nanostructured channel regions disposed on a first portion of the substrate; a first isolation layer disposed between the first and second nanostructured channel regions and in physical contact with the first and second nanostructured channel regions; a gate structure surrounding the first and second nanostructured channel regions", in claim 16 of Pat '037, is interpreted as the same limitation).
Pat '037 does not explicitly disclose a second nanostructured channel region disposed on the first nanostructured channel region; a dielectric layer disposed between and in contact with the first nanostructured channel region and the second nanostructured channel region.
Lin teaches, in at least figures 9, 20, and related text, the device comprising a second nanostructured channel region (2080 over thicker 264, [32], [33], figures) disposed on the first nanostructured channel region (2080 under thicker 264, [32], [33], figures); a dielectric layer (thicker 264, [33]) disposed between and in contact with the first nanostructured channel region (2080 under thicker 264, [32], [33], figures) and the second nanostructured channel region (2080 over thicker 264, [32], [33], figures), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Pat '037 and Lin are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '037 with the specified features of Lin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '037 to have the second nanostructured channel region disposed on the first nanostructured channel region; the dielectric layer disposed between and in contact with the first nanostructured channel region and the second nanostructured channel region, as taught by Lin, for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12], Lin) thereby improving integration of density. as described above.
Regarding claim 2, Pat '037 in view of Lin discloses the semiconductor device of claim 1 as described above.
Lin further teaches, in at least figures 9, 20, and related text, the dielectric layer (thicker 264, [33]) comprises: a bottom surface in contact with a top surface of the first nanostructured channel region (2080 under thicker 264, [32], [33], figures); a top surface in contact with a bottom surface of the second nanostructured channel region (2080 over thicker 264, [32], [33], figures), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Regarding claim 3, Pat '037 in view of Lin discloses the semiconductor device of claim 1 as described above.
Lin further teaches, in at least figures 9, 20, and related text, the gate structure (260, [33]) surrounds the dielectric layer (thicker 264, [33]), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Regarding claim 4, Pat '037 in view of Lin discloses the semiconductor device of claim 1 as described above.
Lin further teaches, in at least figures 9, 20, and related text, the gate structure (260, [33]) comprises a gate dielectric layer (thinner 264, [33], figures), and wherein the gate dielectric layer (thinner 264, [33], figures) is disposed on sidewalls of the first nanostructured channel region (2080 under thicker 264, [32], [33], figures), the second nanostructured channel region (2080 over thicker 264, [32], [33], figures), and the dielectric layer (thicker 264, [33]), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Regarding claim 8, Pat '037 in view of Lin discloses the semiconductor device of claim 1 as described above.
Lin further teaches, in at least figures 9, 20, and related text, a first source/drain region (228, [23]) disposed adjacent to the first nanostructured channel region (2080 under thicker 264, [32], [33], figures); and a second source/drain region (248-1/248-2, [29]) disposed adjacent to the second nanostructured channel region (2080 over thicker 264, [32], [33], figures), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Regarding claim 9, Pat '037 in view of Lin discloses the semiconductor device of claim 8 as described above.
Pat '037 further discloses, in claim 16, an isolation layer disposed between the first and second source/drain regions ("a second isolation disposed between the first and second S/D regions", in claim 16 of Pat '037, is interpreted as the same limitation).
Regarding claim 18, Pat '037 discloses the method of claim 17 as described above.
Pat '037 does not explicitly disclose forming spacers on sidewalls of the second nanostructured layer prior to forming the first and second source/drain regions.
Lin teaches, in at least figures 5, 9, 20, and related text, the method comprising forming spacers (226, [22]) on sidewalls of the second nanostructured layer (2080 over thicker 264, [32], [33], figures) prior to forming the first (228, [23]) and second source/drain regions (248-1/248-2, [29]), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Pat '037 and Lin are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '037 with the specified features of Lin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '037 to have the forming spacers on sidewalls of the second nanostructured layer prior to forming the first and second source/drain regions, as taught by Lin, for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12], Lin) thereby improving integration of density. as described above.
Regarding claim 19, Pat '037 discloses the method of claim 17 as described above.
Pat '037 does not explicitly disclose depositing another dielectric layer on the first source/drain region prior to forming the second source/drain region.
Lin teaches, in at least figures 5, 9, 20, and related text, the method comprising depositing another dielectric layer (242, [25]) on the first source/drain region (228, [23]) prior to forming the second source/drain region (248-1/248-2, [29]), for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12]) thereby improving integration of density.
Pat '037 and Lin are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '037 with the specified features of Lin because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Pat '037 to have the depositing another dielectric layer on the first source/drain region prior to forming the second source/drain region, as taught by Lin, for the purpose of providing local contact feature that directly and vertically couples a source/drain feature of a top multi-gate device to a source/drain feature of a bottom multi-gate device ([12], Lin) thereby improving integration of density. as described above.
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 of U.S. Patent No. 12,166,037 in view of Lin (US 2022/0216340), and further in view of Xie (US 2023/0040712).
Regarding claim 10, Pat '037 in view of Lin discloses the semiconductor device of claim 1 as described above.
Pat '037 in view of Lin does not explicitly disclose an oxide layer disposed between the substrate and the first nanostructured channel region.
Xie teaches, in at least figures 1B, 21, and related text, the device comprising an oxide layer (120, [50]) disposed between the substrate (110, [52]) and the first nanostructured channel region (lower 130, [52], figures), for the purpose of providing isolating layer on substrate ([50]) thereby reducing current leakage through substrate.
Pat '037, Lin, and Xie are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '037 in view of Lin with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '037 in view of Lin to have the oxide layer disposed between the substrate and the first nanostructured channel region, as taught by Xie, for the purpose of providing isolating layer on substrate ([50], Xie) thereby reducing current leakage through substrate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 8 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin (US 2022/0216340).
Regarding claim 1, Lin discloses, in at least figures 9, 17, and related text, a semiconductor device, comprising:
a substrate (202, [14]);
a first nanostructured channel region (2080 under thicker 264, [32], [33], figures) disposed on the substrate (202, [14]);
a second nanostructured channel region (2080 over thicker 264, [32], [33], figures) disposed on the first nanostructured channel region (2080 under thicker 264, [32], [33], figures);
a dielectric layer (thicker 264, [33]) disposed between and in contact with the first nanostructured channel region (2080 under thicker 264, [32], [33], figures) and the second nanostructured channel region (2080 over thicker 264, [32], [33], figures); and
a gate structure (260, [33]) surrounding the first (2080 under thicker 264, [32], [33], figures) and second (2080 over thicker 264, [32], [33], figures) nanostructured channel regions.
Regarding claim 2, Lin discloses the semiconductor device of claim 1 as described above.
Lin further discloses, in at least figures 9, 17, and related text, the dielectric layer (thicker 264, [33]) comprises: a bottom surface in contact with a top surface of the first nanostructured channel region (2080 under thicker 264, [32], [33], figures); a top surface in contact with a bottom surface of the second nanostructured channel region (2080 over thicker 264, [32], [33], figures).
Regarding claim 3, Lin discloses the semiconductor device of claim 1 as described above.
Lin further discloses, in at least figures 9, 20, and related text, the gate structure (260, [33]) surrounds the dielectric layer (thicker 264, [33]).
Regarding claim 4, Lin discloses the semiconductor device of claim 1 as described above.
Lin further discloses, in at least figures 9, 20, and related text, the gate structure (260, [33]) comprises a gate dielectric layer (thinner 264, [33], figures), and wherein the gate dielectric layer (thinner 264, [33], figures) is disposed on sidewalls of the first nanostructured channel region (2080 under thicker 264, [32], [33], figures), the second nanostructured channel region (2080 over thicker 264, [32], [33], figures), and the dielectric layer (thicker 264, [33]).
Regarding claim 8, Lin discloses the semiconductor device of claim 1 as described above.
Lin further discloses, in at least figures 9, 20, and related text, a first source/drain region (228, [23]) disposed adjacent to the first nanostructured channel region (2080 under thicker 264, [32], [33], figures); and a second source/drain region (248-1/248-2, [29]) disposed adjacent to the second nanostructured channel region (2080 over thicker 264, [32], [33], figures).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2022/0216340) in view of Xie (US 2023/0040712).
Regarding claim 10, Lin discloses the semiconductor device of claim 1 as described above.
Lin does not explicitly disclose an oxide layer disposed between the substrate and the first nanostructured channel region.
Xie teaches, in at least figures 1B, 21, and related text, the device comprising an oxide layer (120, [50]) disposed between the substrate (110, [52]) and the first nanostructured channel region (lower 130, [52], figures), for the purpose of providing isolating layer on substrate ([50]) thereby reducing current leakage through substrate.
Lin and Xie are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lin with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lin to have the oxide layer disposed between the substrate and the first nanostructured channel region, as taught by Xie, for the purpose of providing isolating layer on substrate ([50], Xie) thereby reducing current leakage through substrate.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 5 that recite "sidewalls of the first and second nanostructured channel regions comprise curved profiles" in combination with other elements of the base claims 1 and 5.
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 6 that recite "the dielectric layer comprises a sidewall profile with a decreasing slope from a bottom surface of the second nanostructured channel region to a top surface of the first nanostructured channel region" in combination with other elements of the base claims 1 and 6.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 7 that recite "a lower layer portion comprising a first sidewall profile with an increasing slope from a top surface of the first nanostructured channel region towards a bottom surface of the second nanostructured channel region; an upper layer portion comprising a second sidewall profile with a decreasing slope from the bottom surface of the second nanostructured channel region towards the top surface of the first nanostructured channel region" in combination with other elements of the base claims 1 and 7.
Claims 11-16 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 11 that recite "a dielectric layer with a top surface in contact with the second nanostructured channel region and a bottom surface in contact with the gate structure" in combination with other elements of the base claims 11.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 17 and 20 that recite “etching the first nanostructured layer, the dielectric layer, and the second nanostructured layer prior to forming the polysilicon structure" in combination with other elements of the base claims 17 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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