Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 9, 16 and 21
b. Pending: 1-24
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 7/12/2024, 5/22/2025, 10/2/2025 and 11/14/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Jo (US 20240290365) in view of Park et al. (US 20230360689).
Regarding independent claim 1, Jo discloses a stack memory device (Figs. 1-10 describes memory device) comprising:
a command control circuit (14; Fig. 1 and [0023]) configured to:
latch a command and an address in synchronization with a clock signal to generate a latch command and a latch address (Figs. 4-5 and [0047] describes a clock 104 (“CLK”) and command address buffer (CA buffer) 118 may receive a command address signal 120 (“CA<n:0>”). Fig. 6 and [0054] describes that99 flip-flop 160A may latch the command address signal 120 in response to the even clock 102 and the flip-flop 160B may latch the command address signal 120 in response to the odd clock 106),
decode the latch command and the latch address to generate a decoding command that is transmitted through a first interface (Figs. 4-6 all show command decoder 32 and [0047] describes that command decoder 32 may decode the command address and transmit the decoded command (“Output @CMDDEC” corresponding to line 138) to downstream flip-flops 140, such as decoder flip-flop (FF_DEC0) 140A, decoder flip-flop (FF_DEC2) 140B, and eventually decoder flip-flop (FF_DEC1) 140C and decoder flip-flop (FF_DEC3) 140D. The downstream circuit together form the interface before it reaches memory banks), and
encode the decoding command to generate a row control signal and a column control signal that are transmitted through a second interface (Fig. 1 and [0027] describes bank control block 22 which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks 12. Here examiner asserts that communications to and from the memory banks 12 are done via another interface); and
a core control circuit configured to, based on the row control signal and the column control signal, control internal operations performed on a core chip (Fig. 1 and [0027] describes bank control block 22 which facilitates the execution of commands to and from the memory banks 12);
Jo doesn’t disclose a stack memory device;
However, Park teaches a stack memory device (Fig. 13 and [0103] describes a stacked memory device 1000);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Park to Jo in order to provide with semiconductor memory device with improved operation performance as taught by Park ([0006]).
Regarding claim 2, Jo and Park together disclose all the elements of claim 1 as above and through Jo further the first interface is different from the second interface (Figs. 1, 4-6 show two different interfaces).
Regarding claim 3, Jo and Park together disclose all the elements of claim 1 as above and through Jo further the command control circuit (14; Fig. 1 and [0023]) comprises:
a first command latch configured to latch the command in synchronization with the clock signal and output the latched command as a latch command; a second command latch configured to latch the address in synchronization with the clock signal and output the latched address as a latch address (Figs. 4-5 and [0047] describes a clock 104 (“CLK”) and command address buffer (CA buffer) 118 may receive a command address signal 120 (“CA<n:0>”). Fig. 6 and [0054] describes that99 flip-flop 160A may latch the command address signal 120 in response to the even clock 102 and the flip-flop 160B may latch the command address signal 120 in response to the odd clock 106);
a command decoder configured to decode the latch command and the latch address to generate the decoding command (Figs. 4-6 all show command decoder 32 and [0047] describes that command decoder 32 may decode the command address and transmit the decoded command (“Output @CMDDEC” corresponding to line 138) to downstream flip-flops 140, such as decoder flip-flop (FF_DEC0) 140A, decoder flip-flop (FF_DEC2) 140B, and eventually decoder flip-flop (FF_DEC1) 140C and decoder flip-flop (FF_DEC3) 140D); and
a command encoder configured to encode the decoding command to generate the row control signal and the column control signal (Fig. 1 and [0027] describes bank control block 22 which provides the necessary decoding (e.g., row decoder and column decoder), as well as other features, such as timing control and data control, to facilitate the execution of commands to and from the memory banks 12).
Regarding claim 4, Jo and Park together disclose all the elements of claim 1 as above and through Jo further the command control circuit (14; Fig. 1 and [0023]) is configured to: decode the latch command and the latch address to generate a data input control signal to perform a write operation on the core chip ([0035] describes); and decode the latch command and the latch address to generate a data output control signal to perform a read operation on the core chip ([0027] describes write operation) that phase controlled internal clock signal LCLK is supplied to the I/O interface 16, for instance, and is used as a timing signal for determining an output timing of read data).
Regarding claim 5, Jo and Park together disclose all the elements of claim 1 as above and through Jo further a parallelization circuit configured to receive data serially (Fig. 6 and [0053] describes that delay circuitry 164A may send the command address signal 120 to the flip-flop 160A and the flip-flop 160B substantially in parallel to each other), based on a data strobe signal ([0035] describes data strobe signals, generally referred to as DQS signals), when a data input control signal is generated to perform a write operation on the core chip, to generate a write data strobe signal and parallelized internal data ([0035] describes that for write commands, the DQS signals are used as clock signals to capture the corresponding input data. As with the clock signals (Clk_t and Clk_c), the data strobe (DQS) signals may be provided as a differential pair of data strobe signals (DQS_t and DQS_c) to provide differential pair signaling during reads and writes).
Regarding claim 6, Jo and Park together disclose all the elements of claim 5 as above and through Jo further the core control circuit is configured to store the internal data in the core chip, in synchronization with the write data strobe signal, when the write operation on the core chip is performed (Figs. 1, 6 and [0035]).
Regarding claim 7, Jo and Park together disclose all the elements of claim 5 as above and through Park further a serialization circuit configured to receive internal data, from the core control circuit, in parallel and in synchronization with a read data strobe signal, when a data output control signal is generated to perform a read operation on the core chip, to generate a data strobe signal and serialized data (Figs. 3-4, [0061] describes the rising edge multiplexer 350 may serialize data signals DTA, that is, D1, D2, D3, and D4, input in parallel in response to clock signals CK1 to CK4 into one data signal D_TX and output the one data signal D_TX. Specifically, referring to FIG. 4, the rising edge multiplexer 350 may output the data signal D1 in response to the clock signal CK1, output the data signal D2 in response to the clock signal CK2, output the data signal D3 in response to the clock signal CK3, and output the data signal D4 in response to the clock signal CK4. The serial data signal D_TX may be output in response to rising edges of the clock signals CK1, CK2, CK3, and CK4. An example embodiment is not limited thereto, and the rising edge multiplexer 350 may convert N parallel signals into one serial signal D_TX).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Park to modified Jo in order to provide with semiconductor memory device with improved operation performance as taught by Park ([0006]).
Regarding claim 8, Jo and Park together disclose all the elements of claim 7 as above and through Park further the core control circuit is configured to output the internal data from the core chip, in synchronization with the read data strobe signal, when the read operation on the core chip is performed ([0048] describes that data input/output buffer 320 may convert the data DTA provided from the ECC engine 390 into the data signal DQ based on the output clock signal OCLK provided from the clock generation circuit 600 and provide the data signal DQ and the strobe signal DQS to the memory controller 100 in a read operation).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Park to modified Jo in order to provide with semiconductor memory device with improved operation performance as taught by Park ([0006]).
Claims 9-15 recite the similar claim limitations as in claims 1-8 in slightly different format and henceforth rejected the same way.
Claims 16-20 recite the same claim limitations as in claims 1-8 in slightly different format and henceforth rejected the same way.
Regarding independent claim 21, Park discloses a stack memory device (Fig. 13) comprising:
a base chip (Fig. 13 shows base chip 1010); and
a core chip stacked on the base chip and electrically connected to the base chip (Fig. 13 shows core chip 1020 connected to base chip 1010),
wherein the base chip comprises: a command control circuit (Fig. 13 shows base chip 1010 with control logic circuit 1012)configured to:
rest of claim 21 is same as claim 1 and henceforth rejected the same way.
Claims 22-24 recite the similar claim limitations as in claims 2-8 in slightly different format and henceforth rejected the same way.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/10/2026