DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 16-20 are allowed over the prior art of record.
3. The following is an examiner’s statement of reasons for allowance:
4. Regarding claim 16, the prior art of record fail to teach either singly or in combination a method of operating an analog-to-digital converter circuit, the method comprising: and enabling or disabling, by a controller, the comparator by a first enable signal, the first enable signal being generated in response to at least the comparator output signal, the controller being coupled to the comparator.
Response to Arguments
5. Claims 1-15 currently held in abeyance will be allowed upon receipt and approval of the terminal disclaimer by the Office.
Non-Statutory Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
7. Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,094,894 to Chou et al because the claimed invention, claims 1-15 of the present application is a broader version of the claimed invention, claims 1-15 of the U.S.
8. With respect to claim 1, Chou et al disclose in claim 1, an integrated circuit, comprising: a ramp signal generator circuit configured to generate a ramp reference signal; a comparator configured to compare a pixel output signal and the ramp reference signal thereby generating a comparator output signal; a counter coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal; and a control circuit coupled to the comparator, and configured to enable or disable the comparator by a first enable signal, the first enable signal generated in response to at least the comparator output signal. Although the claims at issue are not identical, they are not patentably distinct from each other because an integrated circuit is functionally equivalent to an integrated circuit of the instant invention in that enabling and disabling a counter and a comparator can be used interchangeably as turned on or turned off a counter and a comparator in response to a comparator output signal and an enable signal. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to use an integrated circuit similarly as the instant invention's integrated circuit to enable or disable and/or turn on or turn off the counter and comparator to acquire more precise and accurate signal responses in an imaging device.
9. With respect to claim 2, Chou et al disclose in claim 5, the integrated circuit wherein the comparator comprises: a bias transistor having a gate, a drain and a source, the source of the bias transistor being coupled to a reference voltage supply, and the gate of the bias transistor being configured to receive a bias voltage; and an enable transistor having a gate, a drain and a source, the source of the enable transistor being coupled to the drain of the bias transistor, the gate of the enable transistor being configured to receive the first enable signal, and the drain of the enable transistor being coupled to at least a first node.
10. With respect to claim 3, Chou et al disclose in claim 6, the integrated circuit wherein the comparator further comprises: a first transistor having a gate, a drain and a source, the source of the first transistor being coupled to a voltage supply; and a second transistor having a gate, a drain and a source, each of the gate of the first transistor, the drain of the first transistor and the drain of the second transistor are coupled together, the source of the second transistor being coupled to the first node and the drain of the enable transistor, and the gate of the second transistor being configured to receive the ramp reference signal.
11. With respect to claim 4, Chou et al disclose in claim 7, the integrated circuit wherein the comparator further comprises: a third transistor having a gate, a drain and a source, the source of the third transistor being coupled to the voltage supply, and the gate of the third transistor being coupled to the gate of the first transistor, the drain of the first transistor and the drain of the second transistor; and a fourth transistor having a gate, a drain and a source, the drain of the third transistor being coupled to the drain of the fourth transistor at an output node of the comparator, the source of the fourth transistor being coupled to the first node, the drain of the enable transistor, and the source of the second transistor, and the gate of the fourth transistor being configured to receive the pixel output signal.
12. With respect to claim 5, Chou et al disclose in claim 4, the integrated circuit wherein the control circuit comprises: a NAND gate comprising a first input terminal coupled to the comparator and configured to receive the comparator output signal, a second input terminal configured to receive a control signal, and a first output terminal coupled to the comparator and configured to generate the first enable signal in response to at least one of the comparator output signals or the control signal.
13. With respect to claim 6, Chou et al disclose in claim 2, the integrated circuit further comprising: a pixel circuit coupled to the comparator, and configured to generate the pixel output signal.
14. With respect to claim 7, Chou et al disclose in claim 3, the integrated circuit further comprising: an amplifier coupled to the pixel circuit, the comparator and the control circuit, the amplifier being enabled or disabled by the first enable signal, the amplifier configured to amplify the pixel output signal.
15. With respect to claim 8, Chou et al disclose in claim 8, an integrated circuit comprising: an analog-to-digital converter circuit configured to convert a first analog pixel output signal to a digital signal, wherein the analog-to-digital converter circuit comprises: a comparator configured to generate a comparator output signal in response to a second analog pixel output signal and a reference signal; a counter coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal; and a control circuit coupled to the comparator, and configured to enable or disable the comparator by a first enable signal, the first enable signal generated in response to at least one of the comparator output signal or a control signal. Although the claims at issue are not identical, they are not patentably distinct from each other because an integrated circuit is functionally equivalent to an integrated circuit of the instant invention in that enabling and disabling a counter and a comparator can be used interchangeably as turned on or turned off a counter and a comparator in response to a comparator output signal and an enable signal. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to use an integrated circuit similarly as the instant invention's integrated circuit to enable or disable and/or turn on or turn off the counter and comparator to acquire more precise and accurate signal responses in an imaging device.
16. With respect to claim 9, Chou et al disclose in claim 9, the integrated circuit wherein the analog-to-digital converter circuit comprises: an amplifier coupled to the comparator and the control circuit, the amplifier being enabled or disabled by a second enable signal, the amplifier being configured to generate the second analog pixel output signal in response to the first analog pixel output signal.
17. With respect to claim 10, Chou et al disclose in claim 10, the integrated circuit further comprising: a pixel bias circuit coupled to at least one of the amplifier and the control circuit, wherein the control circuit is further configured to enable or disable the pixel bias circuit in response to a third enable signal.
18. With respect to claim 11, Chou et al disclose in claim 11, the integrated circuit wherein the pixel bias circuit comprises: a first transistor having a gate, a drain and a source, the source of the first transistor being coupled to a reference voltage supply, and the gate of the first transistor being configured to receive a bias voltage signal; and a second transistor having a gate, a drain and a source, the source of the second transistor being coupled to the drain of the first transistor, the gate of the second transistor being coupled to the control circuit and configured to receive the third enable signal, and the drain of the second transistor being coupled to at least an input of the amplifier.
19. With respect to claim 12, Chou et al disclose in claim 12, the integrated circuit wherein the first transistor and the second transistor are configured to set the first analog pixel output signal in response to the third enable signal and the bias voltage signal.
20. With respect to claim 13, Chou et al disclose in claim 13, the integrated circuit wherein the control circuit comprises: a first NAND gate comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal of the first NAND gate being coupled to at least the comparator and configured to receive the comparator output signal, the second input terminal of the first NAND gate being configured to receive the control signal, and the first output terminal of the first NAND gate being coupled to the comparator and configured to generate the first enable signal in response to the comparator output signal and the control signal.
21. With respect to claim 14, Chou et al disclose in claim 14, the integrated circuit wherein the control circuit further comprises: a second NAND gate comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal of the second NAND gate being coupled to the comparator and the first input terminal of the first NAND gate and configured to receive the comparator output signal, the second input terminal of the second NAND gate being coupled to the second input terminal of the first NAND gate and configured to receive the control signal, and the first output terminal of the second NAND gate being coupled to the gate of the second transistor and configured to generate the third enable signal in response to the comparator output signal and the control signal.
22. With respect to claim 15, Chou et al disclose in claim 15, the integrated circuit wherein the control circuit further comprises: a third NAND gate comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal of the third NAND gate being coupled to the comparator, the first input terminal of the first NAND gate and the first input terminal of the second NAND gate and configured to receive the comparator output signal, the second input terminal of the third NAND gate being coupled to the second input terminal of the first NAND gate, the second input terminal of the second NAND gate and configured to receive the control signal, and the first output terminal of the third NAND gate being coupled to the amplifier and configured to generate the second enable signal in response to the comparator output signal and the control signal.
Conclusion
23. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
24. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DON J WILLIAMS whose telephone number is (571)272-8538. The examiner can normally be reached M-F 8 a.m.-5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Epps can be reached at 571-272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DON J WILLIAMS/Examiner, Art Unit 2878
/GEORGIA Y EPPS/Supervisory Patent Examiner, Art Unit 2878
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