Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 2nd, 2026 has been entered.
Response to Arguments
2. Applicant’s arguments, filed April 2nd, 2026, with respect to the rejections of claims 1, 3, 6, and 9 under McCarthy and Kinzinger have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Sukhomlinov (US 2019/0044971).
3. Applicant’s arguments, filed April 2nd, 2026, with respect to the 35 U.S.C. 103 rejections of claim 10 and its dependents have been fully considered and are persuasive in light of the claim amendments. The claim rejections have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 3, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Sukhomlinov et al (US 2019/0044971, herein Sukhomlinov) in view of Kinzinger (US 2019/0065198).
Regarding claim 1, Sukhomlinov teaches a integrated circuit comprising:
a memory configured to store instructions ([0021] memory); and
a processor device coupled to the memory and configured to execute the instructions ([0021], CPU 116), the processor device configured to:
execute a discontinuity instruction that corresponds to a transition from execution according to a first stack to execution according to a second stack, wherein the discontinuity instruction specifies a destination address ([0023], [0029], [0091-0092], switch to a second callee stack in response to executing a call to a callee function);
determine whether the destination address stores an entry instruction that corresponds to the discontinuity instruction ([0018], starting address of stack, [0021-0024], function call corresponding to different address space); and
based on the destination address storing the entry instruction, begin execution at the destination address (Fig 5, [0018], [0061], start execution at stored address corresponding to a function call).
Sukhomlinov fails to teach the execution being according to stack pointers.
Kinzinger teaches an integrated circuit configured to identify an entry instruction corresponds to a discontinuity instruction that corresponds to a transition from execution according to a first stack pointer to execution according to a second stack pointer ([0016], call instructions & address operands, [0018-0019], register stack entry addressing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sukhomlinov and Kinzinger to utilize explicit stack pointers. While Sukhomlinov does not explicitly disclose that the technique for switching stacks may utilize pointers, a pointer corresponding to a function or other address is a routine and conventional aspect of the microprocessor art. Therefore, utilizing stack pointers would merely entail a simple substitution of known prior art elements to achieve predictable results, and would have been obvious to one of ordinary skill in the art.
Regarding claim 3, the combination of Sukhomlinov and Kinzinger teaches the circuit of claim 1, wherein the processor device is configured to generate a fault based on the destination address not storing the entry instruction (Sukhomlinov [0029], generate exception based on call to invalid address space or other privileged locations [0038], [0040], fault condition and exception handling).
Regarding claim 6, the combination of Sukhomlinov and Kinzinger teaches the circuit of claim 1, wherein: the processor device is associated with an instruction set; and the entry instruction is distinct from each other combination of instruction and/or data in the instruction set (Kinzinger [0012], instruction set opcode addressing).
Regarding claim 9, the combination of Sukhomlinov and Kinzinger teaches the circuit of claim 1, wherein the discontinuity instruction is a call or branch (Sukhomlinov [0022] call instruction).
Allowable Subject Matter
5. Claims 10 and 12-23 are allowed.
6. Claims 2, 4-5, and 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Neiger (US 2022/0283813) discloses a processor that switches to a stack using a branch instruction in response to an inter-privilege-level system call.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/Primary Examiner, Art Unit 2183
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